49510c5020
All instructions that can raise fp exceptions also read FPCR, with the only other instructions that interact with it being the MSR/MRS to write/read FPCR. Introducing an FPCR register also requires adjusting invalidateWindowsRegisterPairing in AArch64FrameLowering.cpp to use the encoded value of registers instead of their enum value, as the enum value is based on the alphabetical order of register names and now FPCR is placed between FP and LR. This change unfortunately means a large number of mir tests need to be adjusted due to instructions now requiring an implicit fpcr operand to be present. Differential Revision: https://reviews.llvm.org/D121929
38 lines
1.3 KiB
YAML
38 lines
1.3 KiB
YAML
# RUN: llc -mcpu=exynos-m5 -mtriple=aarch64 -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o /dev/null 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# CHECK-LABEL: ********** MI Scheduling **********
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# CHECK: SU(0): %0:fpr128 = COPY $q1
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# CHECK-NEXT: # preds left : 0
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# CHECK-NEXT: # succs left : 1
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 2
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# CHECK-NEXT: Depth : 0
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# CHECK-NEXT: Height : 12
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(1): Data Latency=2 Reg=%0
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU(1): %1:fpr32 = FMINVv4i32v %0:fpr128, implicit $fpcr
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# CHECK-NEXT: # preds left : 1
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# CHECK-NEXT: # succs left : 1
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 8
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# CHECK-NEXT: Depth : 2
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# CHECK-NEXT: Height : 10
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# CHECK-NEXT: Predecessors:
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# CHECK-NEXT: SU(0): Data Latency=2 Reg=%0
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(2): Data Latency=8 Reg=%1
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# CHECK-NEXT: Single Issue : false;
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name: test_qform_virtreg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0, $q1
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%0:fpr128 = COPY $q1
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%1:fpr32 = FMINVv4i32v %0:fpr128, implicit $fpcr
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$s0 = COPY %1
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RET_ReallyLR implicit $s0
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