db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
112 lines
4.0 KiB
LLVM
112 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
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define <1 x i64> @v1i64(<1 x i64> %a) {
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; CHECK-LABEL: v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
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; CHECK-NEXT: ret
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%b = lshr <1 x i64> %a, <i64 31>
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%c = and <1 x i64> %b, <i64 4294967297>
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%d = mul nuw <1 x i64> %c, <i64 4294967295>
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ret <1 x i64> %d
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}
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define <2 x i64> @v2i64(<2 x i64> %a) {
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; CHECK-LABEL: v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-NEXT: ret
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%b = lshr <2 x i64> %a, <i64 31, i64 31>
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%c = and <2 x i64> %b, <i64 4294967297, i64 4294967297>
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%d = mul nuw <2 x i64> %c, <i64 4294967295, i64 4294967295>
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ret <2 x i64> %d
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}
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define <2 x i32> @v2i32(<2 x i32> %a) {
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; CHECK-LABEL: v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
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; CHECK-NEXT: ret
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%b = lshr <2 x i32> %a, <i32 15, i32 15>
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%c = and <2 x i32> %b, <i32 65537, i32 65537>
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%d = mul nuw <2 x i32> %c, <i32 65535, i32 65535>
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ret <2 x i32> %d
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}
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define <4 x i32> @v4i32(<4 x i32> %a) {
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; CHECK-LABEL: v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
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; CHECK-NEXT: ret
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%b = lshr <4 x i32> %a, <i32 15, i32 15, i32 15, i32 15>
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%c = and <4 x i32> %b, <i32 65537, i32 65537, i32 65537, i32 65537>
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%d = mul nuw <4 x i32> %c, <i32 65535, i32 65535, i32 65535, i32 65535>
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ret <4 x i32> %d
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}
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define <8 x i32> @v8i32(<8 x i32> %a) {
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; CHECK-LABEL: v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
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; CHECK-NEXT: cmlt v1.8h, v1.8h, #0
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; CHECK-NEXT: ret
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%b = lshr <8 x i32> %a, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
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%c = and <8 x i32> %b, <i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537>
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%d = mul nuw <8 x i32> %c, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
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ret <8 x i32> %d
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}
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define <4 x i16> @v4i16(<4 x i16> %a) {
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; CHECK-LABEL: v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
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; CHECK-NEXT: ret
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%b = lshr <4 x i16> %a, <i16 7, i16 7, i16 7, i16 7>
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%c = and <4 x i16> %b, <i16 257, i16 257, i16 257, i16 257>
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%d = mul nuw <4 x i16> %c, <i16 255, i16 255, i16 255, i16 255>
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ret <4 x i16> %d
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}
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define <8 x i16> @v8i16(<8 x i16> %a) {
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; CHECK-LABEL: v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: ret
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%b = lshr <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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%c = and <8 x i16> %b, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
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%d = mul nuw <8 x i16> %c, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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ret <8 x i16> %d
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}
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define <8 x i8> @v8i8(<8 x i8> %a) {
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; CHECK-LABEL: v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.8b, #17
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; CHECK-NEXT: ushr v0.8b, v0.8b, #3
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; CHECK-NEXT: movi v2.8b, #15
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: mul v0.8b, v0.8b, v2.8b
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; CHECK-NEXT: ret
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%b = lshr <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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%c = and <8 x i8> %b, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17>
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%d = mul nuw <8 x i8> %c, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
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ret <8 x i8> %d
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}
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define <16 x i8> @v16i8(<16 x i8> %a) {
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; CHECK-LABEL: v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.16b, #17
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; CHECK-NEXT: ushr v0.16b, v0.16b, #3
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; CHECK-NEXT: movi v2.16b, #15
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: mul v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%b = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
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%c = and <16 x i8> %b, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17>
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%d = mul nuw <16 x i8> %c, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
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ret <16 x i8> %d
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}
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