a574ef6176
When an sreg sub-register of a q register was spilled, AArch64InstrInfo::foldMemoryOperandImpl would emit a spill of a d register, which gives the wrong result when the target is big-endian as the following q register fill will put the value in the top half. Fix this by greatly simplifying the existing code for widening the spill to only handle wzr to xzr widening, as the default result we get if the function returns nullptr is already that a widened spill will be emitted.
135 lines
5.1 KiB
LLVM
135 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- -aarch64-enable-sink-fold=true | FileCheck %s
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declare float @llvm.pow.f32(float, float)
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declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
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declare double @llvm.pow.f64(double, double)
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declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)
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define float @pow_f32_one_fourth_fmf(float %x) nounwind {
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; CHECK-LABEL: pow_f32_one_fourth_fmf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fsqrt s0, s0
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; CHECK-NEXT: fsqrt s0, s0
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; CHECK-NEXT: ret
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%r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)
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ret float %r
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}
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define double @pow_f64_one_fourth_fmf(double %x) nounwind {
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; CHECK-LABEL: pow_f64_one_fourth_fmf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fsqrt d0, d0
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; CHECK-NEXT: fsqrt d0, d0
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; CHECK-NEXT: ret
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%r = call nsz ninf afn double @llvm.pow.f64(double %x, double 2.5e-01)
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ret double %r
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}
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define <4 x float> @pow_v4f32_one_fourth_fmf(<4 x float> %x) nounwind {
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; CHECK-LABEL: pow_v4f32_one_fourth_fmf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fsqrt v0.4s, v0.4s
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; CHECK-NEXT: fsqrt v0.4s, v0.4s
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; CHECK-NEXT: ret
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%r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>)
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ret <4 x float> %r
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}
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define <2 x double> @pow_v2f64_one_fourth_fmf(<2 x double> %x) nounwind {
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; CHECK-LABEL: pow_v2f64_one_fourth_fmf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fsqrt v0.2d, v0.2d
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; CHECK-NEXT: fsqrt v0.2d, v0.2d
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; CHECK-NEXT: ret
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%r = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>)
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ret <2 x double> %r
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}
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define float @pow_f32_one_fourth_not_enough_fmf(float %x) nounwind {
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; CHECK-LABEL: pow_f32_one_fourth_not_enough_fmf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s1, #0.25000000
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; CHECK-NEXT: b powf
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%r = call afn ninf float @llvm.pow.f32(float %x, float 2.5e-01)
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ret float %r
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}
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define double @pow_f64_one_fourth_not_enough_fmf(double %x) nounwind {
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; CHECK-LABEL: pow_f64_one_fourth_not_enough_fmf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d1, #0.25000000
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; CHECK-NEXT: b pow
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%r = call nsz ninf double @llvm.pow.f64(double %x, double 2.5e-01)
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ret double %r
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}
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define <4 x float> @pow_v4f32_one_fourth_not_enough_fmf(<4 x float> %x) nounwind {
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; CHECK-LABEL: pow_v4f32_one_fourth_not_enough_fmf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #48
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; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: mov s0, v0.s[1]
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; CHECK-NEXT: fmov s1, #0.25000000
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; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
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; CHECK-NEXT: bl powf
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; CHECK-NEXT: fmov s1, #0.25000000
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: bl powf
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; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: mov v0.s[1], v1.s[0]
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; CHECK-NEXT: fmov s1, #0.25000000
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; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: mov s0, v0.s[2]
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; CHECK-NEXT: bl powf
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; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: mov v1.s[2], v0.s[0]
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; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: mov s0, v0.s[3]
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; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: fmov s1, #0.25000000
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; CHECK-NEXT: bl powf
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; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
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; CHECK-NEXT: mov v1.s[3], v0.s[0]
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: add sp, sp, #48
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; CHECK-NEXT: ret
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%r = call afn nsz <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>)
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ret <4 x float> %r
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}
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define <2 x double> @pow_v2f64_one_fourth_not_enough_fmf(<2 x double> %x) nounwind {
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; CHECK-LABEL: pow_v2f64_one_fourth_not_enough_fmf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #48
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; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: mov d0, v0.d[1]
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; CHECK-NEXT: fmov d1, #0.25000000
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; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
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; CHECK-NEXT: bl pow
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; CHECK-NEXT: fmov d1, #0.25000000
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: bl pow
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; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
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; CHECK-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-NEXT: add sp, sp, #48
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; CHECK-NEXT: ret
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%r = call nsz nnan reassoc <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>)
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ret <2 x double> %r
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}
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