Files
clang-p2996/llvm/test/CodeGen/AArch64/pr55201.ll
Tuan Chuong Goh 8eeabf674c [AArch64] Add funnel shift lowering for SelectionDAG
Consider FSHR legal if shift amount is constant
Lower FSHL to FSHR if shift amount is constant

Differential Revision: https://reviews.llvm.org/D155565
2023-07-28 11:56:25 +01:00

18 lines
479 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
define i32 @f(i32 %x) {
; CHECK-LABEL: f:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, w0, #0x1
; CHECK-NEXT: extr w8, w8, w0, #27
; CHECK-NEXT: and w0, w8, #0xffffffe1
; CHECK-NEXT: ret
%or1 = or i32 %x, 1
%sh1 = shl i32 %or1, 5
%sh2 = lshr i32 %x, 27
%1 = and i32 %sh2, 1
%r = or i32 %sh1, %1
ret i32 %r
}