db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
31 lines
1.0 KiB
LLVM
31 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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; This used to hit an assertion caused by dagcombine merge store.
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; When the store memVT is v1f32 and the other store to be merged
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; is f32, we need to build vector for the f32 store.
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define void @f(<1 x float> %a, i64 %b) {
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; CHECK-LABEL: f:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: bfi x9, x0, #2, #1
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; CHECK-NEXT: str d1, [sp]
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; CHECK-NEXT: ldr s1, [x9]
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; CHECK-NEXT: mov v1.s[1], v0.s[0]
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; CHECK-NEXT: str d1, [sp, #8]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%P = alloca i64
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%E = extractelement <2 x float> <float 0.5, float 1.0>, i64 %b
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%G = getelementptr <1 x float>, ptr %P, i64 1
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store float %E, ptr %P
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store <1 x float> %a, ptr %G
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ret void
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}
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