db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
35 lines
1.0 KiB
LLVM
35 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
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; RUN: llc < %s -mtriple=aarch64 --global-isel | FileCheck %s --check-prefix=GISEL
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define i35 @f(i35 %0) {
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; CHECK-LABEL: f:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sbfx x8, x0, #0, #35
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; CHECK-NEXT: mov w9, #1 // =0x1
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; CHECK-NEXT: sdiv x10, x9, x8
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; CHECK-NEXT: msub x8, x10, x8, x9
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; CHECK-NEXT: clz x8, x8
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; CHECK-NEXT: sub x8, x8, #29
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; CHECK-NEXT: ubfx x0, x8, #5, #30
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; CHECK-NEXT: ret
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;
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; GISEL-LABEL: f:
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; GISEL: // %bb.0:
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; GISEL-NEXT: sbfx x8, x0, #0, #35
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; GISEL-NEXT: mov w9, #1 // =0x1
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; GISEL-NEXT: sdiv x10, x9, x8
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; GISEL-NEXT: msub x8, x10, x8, x9
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; GISEL-NEXT: and x8, x8, #0x7ffffffff
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; GISEL-NEXT: clz x8, x8
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; GISEL-NEXT: sub x8, x8, #29
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; GISEL-NEXT: ubfx x0, x8, #5, #30
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; GISEL-NEXT: ret
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%2 = srem i35 1, %0
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%3 = call i35 @llvm.ctlz.i35(i35 %2, i1 false)
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%4 = lshr i35 %3, 5
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ret i35 %4
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}
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declare i35 @llvm.ctlz.i35(i35, i1 immarg)
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