3a894fd90b
As suggested in D12425 it would be better for the readcyclecounter function on ARM architecture to use the CNTVCT_EL0 register (Counter-timer Virtual Count register) instead of the PMCCNTR_EL0 (Performance Monitors Cycle Count Register) because the PMCCNTR_EL0 is a PMU register which, depending on the configuration, it might always return zeroes and it doesn't guaranteed to always be increased. Differential Revision: https://reviews.llvm.org/D136999
14 lines
329 B
LLVM
14 lines
329 B
LLVM
; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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define i64 @test_readcyclecounter() nounwind {
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; CHECK-LABEL: test_readcyclecounter:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mrs x0, CNTVCT_EL0
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; CHECK-NEXT: ret
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%tmp0 = call i64 @llvm.readcyclecounter()
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ret i64 %tmp0
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}
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declare i64 @llvm.readcyclecounter()
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