6288f36c16
This tries to fill in the basic vector handling for sadd_sat/uadd_sat and ssub_sat/usub_sat. It just handles the basics, marking legal types and clamping illegally sized vectors to legal ones.
147 lines
4.7 KiB
LLVM
147 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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declare i4 @llvm.sadd.sat.i4(i4, i4)
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declare i8 @llvm.sadd.sat.i8(i8, i8)
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declare i16 @llvm.sadd.sat.i16(i16, i16)
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declare i32 @llvm.sadd.sat.i32(i32, i32)
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declare i64 @llvm.sadd.sat.i64(i64, i64)
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declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-SD-LABEL: func:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: adds w8, w0, w1
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; CHECK-SD-NEXT: asr w9, w8, #31
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; CHECK-SD-NEXT: eor w9, w9, #0x80000000
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; CHECK-SD-NEXT: csel w0, w9, w8, vs
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #-2147483648 // =0x80000000
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; CHECK-GI-NEXT: adds w9, w0, w1
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; CHECK-GI-NEXT: cset w10, vs
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; CHECK-GI-NEXT: add w8, w8, w9, asr #31
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; CHECK-GI-NEXT: tst w10, #0x1
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; CHECK-GI-NEXT: csel w0, w8, w9, ne
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; CHECK-GI-NEXT: ret
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
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ret i32 %tmp;
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; CHECK-SD-LABEL: func2:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: adds x8, x0, x1
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; CHECK-SD-NEXT: asr x9, x8, #63
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; CHECK-SD-NEXT: eor x9, x9, #0x8000000000000000
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; CHECK-SD-NEXT: csel x0, x9, x8, vs
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func2:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
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; CHECK-GI-NEXT: adds x9, x0, x1
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; CHECK-GI-NEXT: cset w10, vs
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; CHECK-GI-NEXT: add x8, x8, x9, asr #63
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; CHECK-GI-NEXT: tst w10, #0x1
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; CHECK-GI-NEXT: csel x0, x8, x9, ne
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; CHECK-GI-NEXT: ret
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%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
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ret i64 %tmp;
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}
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define i16 @func16(i16 %x, i16 %y) nounwind {
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; CHECK-SD-LABEL: func16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sxth w8, w0
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; CHECK-SD-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-SD-NEXT: add w8, w8, w1, sxth
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; CHECK-SD-NEXT: cmp w8, w9
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; CHECK-SD-NEXT: csel w8, w8, w9, lt
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; CHECK-SD-NEXT: mov w9, #-32768 // =0xffff8000
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; CHECK-SD-NEXT: cmn w8, #8, lsl #12 // =32768
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; CHECK-SD-NEXT: csel w0, w8, w9, gt
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sxth w8, w1
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; CHECK-GI-NEXT: add w8, w8, w0, sxth
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; CHECK-GI-NEXT: sxth w9, w8
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; CHECK-GI-NEXT: asr w10, w9, #15
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; CHECK-GI-NEXT: cmp w8, w9
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; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
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; CHECK-GI-NEXT: csel w0, w10, w8, ne
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; CHECK-GI-NEXT: ret
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%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
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ret i16 %tmp;
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}
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define i8 @func8(i8 %x, i8 %y) nounwind {
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; CHECK-SD-LABEL: func8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sxtb w9, w0
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; CHECK-SD-NEXT: mov w8, #127 // =0x7f
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; CHECK-SD-NEXT: add w9, w9, w1, sxtb
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; CHECK-SD-NEXT: cmp w9, #127
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; CHECK-SD-NEXT: csel w8, w9, w8, lt
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; CHECK-SD-NEXT: mov w9, #-128 // =0xffffff80
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; CHECK-SD-NEXT: cmn w8, #128
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; CHECK-SD-NEXT: csel w0, w8, w9, gt
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sxtb w8, w1
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; CHECK-GI-NEXT: add w8, w8, w0, sxtb
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; CHECK-GI-NEXT: sxtb w9, w8
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; CHECK-GI-NEXT: asr w10, w9, #7
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; CHECK-GI-NEXT: cmp w8, w9
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; CHECK-GI-NEXT: sub w10, w10, #128
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; CHECK-GI-NEXT: csel w0, w10, w8, ne
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; CHECK-GI-NEXT: ret
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%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
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ret i8 %tmp;
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}
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define i4 @func3(i4 %x, i4 %y) nounwind {
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; CHECK-SD-LABEL: func3:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: lsl w9, w1, #28
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; CHECK-SD-NEXT: sbfx w10, w0, #0, #4
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; CHECK-SD-NEXT: mov w8, #7 // =0x7
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; CHECK-SD-NEXT: add w9, w10, w9, asr #28
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; CHECK-SD-NEXT: cmp w9, #7
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; CHECK-SD-NEXT: csel w8, w9, w8, lt
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; CHECK-SD-NEXT: mov w9, #-8 // =0xfffffff8
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; CHECK-SD-NEXT: cmn w8, #8
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; CHECK-SD-NEXT: csel w0, w8, w9, gt
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func3:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sbfx w8, w0, #0, #4
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; CHECK-GI-NEXT: sbfx w9, w1, #0, #4
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; CHECK-GI-NEXT: add w8, w8, w9
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; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
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; CHECK-GI-NEXT: asr w10, w9, #3
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; CHECK-GI-NEXT: cmp w8, w9
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; CHECK-GI-NEXT: add w10, w10, #8
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; CHECK-GI-NEXT: csel w0, w10, w8, ne
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; CHECK-GI-NEXT: ret
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%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
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ret i4 %tmp;
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}
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define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: vec:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqadd v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%tmp = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
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ret <4 x i32> %tmp;
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}
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