db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
216 lines
6.5 KiB
LLVM
216 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
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; Compare if negative and select of constants where one constant is zero.
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define i32 @neg_sel_constants(i32 %a) {
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; CHECK-LABEL: neg_sel_constants:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #5 // =0x5
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; CHECK-NEXT: and w0, w8, w0, asr #31
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; CHECK-NEXT: ret
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%tmp.1 = icmp slt i32 %a, 0
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%retval = select i1 %tmp.1, i32 5, i32 0
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ret i32 %retval
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}
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; Compare if negative and select of constants where one constant is zero and the other is a single bit.
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define i32 @neg_sel_special_constant(i32 %a) {
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; CHECK-LABEL: neg_sel_special_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w8, w0, #22
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; CHECK-NEXT: and w0, w8, #0x200
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; CHECK-NEXT: ret
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%tmp.1 = icmp slt i32 %a, 0
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%retval = select i1 %tmp.1, i32 512, i32 0
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ret i32 %retval
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}
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; Compare if negative and select variable or zero.
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define i32 @neg_sel_variable_and_zero(i32 %a, i32 %b) {
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; CHECK-LABEL: neg_sel_variable_and_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w1, w0, asr #31
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; CHECK-NEXT: ret
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%tmp.1 = icmp slt i32 %a, 0
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%retval = select i1 %tmp.1, i32 %b, i32 0
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ret i32 %retval
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}
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; Compare if not positive and select the same variable as being compared: smin(a, 0).
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define i32 @not_pos_sel_same_variable(i32 %a) {
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; CHECK-LABEL: not_pos_sel_same_variable:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w0, w0, asr #31
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; CHECK-NEXT: ret
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%tmp = icmp slt i32 %a, 1
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%min = select i1 %tmp, i32 %a, i32 0
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ret i32 %min
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}
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; Flipping the comparison condition can be handled by getting the bitwise not of the sign mask.
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; Compare if positive and select of constants where one constant is zero.
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define i32 @pos_sel_constants(i32 %a) {
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; CHECK-LABEL: pos_sel_constants:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #5 // =0x5
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; CHECK-NEXT: bic w0, w8, w0, asr #31
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; CHECK-NEXT: ret
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%tmp.1 = icmp sgt i32 %a, -1
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%retval = select i1 %tmp.1, i32 5, i32 0
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ret i32 %retval
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}
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; Compare if positive and select of constants where one constant is zero and the other is a single bit.
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define i32 @pos_sel_special_constant(i32 %a) {
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; CHECK-LABEL: pos_sel_special_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #512 // =0x200
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; CHECK-NEXT: bic w0, w8, w0, lsr #22
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; CHECK-NEXT: ret
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%tmp.1 = icmp sgt i32 %a, -1
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%retval = select i1 %tmp.1, i32 512, i32 0
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ret i32 %retval
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}
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; Compare if positive and select variable or zero.
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define i32 @pos_sel_variable_and_zero(i32 %a, i32 %b) {
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; CHECK-LABEL: pos_sel_variable_and_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic w0, w1, w0, asr #31
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; CHECK-NEXT: ret
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%tmp.1 = icmp sgt i32 %a, -1
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%retval = select i1 %tmp.1, i32 %b, i32 0
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ret i32 %retval
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}
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; Compare if not negative or zero and select the same variable as being compared: smax(a, 0).
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define i32 @not_neg_sel_same_variable(i32 %a) {
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; CHECK-LABEL: not_neg_sel_same_variable:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic w0, w0, w0, asr #31
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; CHECK-NEXT: ret
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%tmp = icmp sgt i32 %a, 0
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%min = select i1 %tmp, i32 %a, i32 0
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ret i32 %min
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}
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; https://llvm.org/bugs/show_bug.cgi?id=31175
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; ret = (x-y) > 0 ? x-y : 0
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define i32 @PR31175(i32 %x, i32 %y) {
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; CHECK-LABEL: PR31175:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w8, w0, w1
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; CHECK-NEXT: bic w0, w8, w8, asr #31
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; CHECK-NEXT: ret
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%sub = sub nsw i32 %x, %y
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%cmp = icmp sgt i32 %sub, 0
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%sel = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sel
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}
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define i8 @sel_shift_bool_i8(i1 %t) {
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; CHECK-LABEL: sel_shift_bool_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-128 // =0xffffff80
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: csel w0, w8, wzr, ne
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; CHECK-NEXT: ret
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%shl = select i1 %t, i8 128, i8 0
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ret i8 %shl
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}
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define i16 @sel_shift_bool_i16(i1 %t) {
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; CHECK-LABEL: sel_shift_bool_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #128 // =0x80
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: csel w0, w8, wzr, ne
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; CHECK-NEXT: ret
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%shl = select i1 %t, i16 128, i16 0
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ret i16 %shl
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}
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define i32 @sel_shift_bool_i32(i1 %t) {
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; CHECK-LABEL: sel_shift_bool_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #64 // =0x40
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: csel w0, w8, wzr, ne
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; CHECK-NEXT: ret
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%shl = select i1 %t, i32 64, i32 0
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ret i32 %shl
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}
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define i64 @sel_shift_bool_i64(i1 %t) {
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; CHECK-LABEL: sel_shift_bool_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #65536 // =0x10000
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; CHECK-NEXT: tst w0, #0x1
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; CHECK-NEXT: csel x0, x8, xzr, ne
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; CHECK-NEXT: ret
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%shl = select i1 %t, i64 65536, i64 0
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ret i64 %shl
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}
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define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
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; CHECK-LABEL: sel_shift_bool_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.16b, v0.16b, #7
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; CHECK-NEXT: movi v1.16b, #128
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%shl = select <16 x i1> %t, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>, <16 x i8> zeroinitializer
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ret <16 x i8> %shl
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}
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define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {
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; CHECK-LABEL: sel_shift_bool_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-NEXT: movi v1.8h, #128
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; CHECK-NEXT: shl v0.8h, v0.8h, #15
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; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%shl= select <8 x i1> %t, <8 x i16> <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>, <8 x i16> zeroinitializer
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ret <8 x i16> %shl
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}
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define <4 x i32> @sel_shift_bool_v4i32(<4 x i1> %t) {
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; CHECK-LABEL: sel_shift_bool_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-NEXT: movi v1.4s, #64
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; CHECK-NEXT: shl v0.4s, v0.4s, #31
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; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%shl = select <4 x i1> %t, <4 x i32> <i32 64, i32 64, i32 64, i32 64>, <4 x i32> zeroinitializer
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ret <4 x i32> %shl
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}
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define <2 x i64> @sel_shift_bool_v2i64(<2 x i1> %t) {
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; CHECK-LABEL: sel_shift_bool_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v0.2d, v0.2s, #0
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; CHECK-NEXT: mov w8, #65536 // =0x10000
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: shl v0.2d, v0.2d, #63
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; CHECK-NEXT: cmlt v0.2d, v0.2d, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%shl = select <2 x i1> %t, <2 x i64> <i64 65536, i64 65536>, <2 x i64> zeroinitializer
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ret <2 x i64> %shl
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}
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