884b051a42
With special case with Add constant is 0. Original message: We can support these by changing the sext promotion to -zext(-C) and replacing a sgt check with ugt. Reframing the logic in terms of how the unsigned range are affected. More comments in the patch. The new cases check isLegalAddImmediate to avoid some regressions in lit tests.
405 lines
12 KiB
LLVM
405 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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; https://bugs.llvm.org/show_bug.cgi?id=38149
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; We are truncating from wider width, and then sign-extending
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; back to the original width. Then we equality-comparing orig and src.
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; If they don't match, then we had signed truncation during truncation.
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; This can be expressed in a several ways in IR:
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; trunc + sext + icmp eq <- not canonical
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; shl + ashr + icmp eq
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; add + icmp uge/ugt
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; add + icmp ult/ule
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; However only the simplest form (with two shifts) gets lowered best.
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; ---------------------------------------------------------------------------- ;
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; shl + ashr + icmp eq
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; ---------------------------------------------------------------------------- ;
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define i1 @shifts_eqcmp_i16_i8(i16 %x) nounwind {
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; CHECK-LABEL: shifts_eqcmp_i16_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w0
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; CHECK-NEXT: and w8, w8, #0xffff
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; CHECK-NEXT: cmp w8, w0, uxth
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = shl i16 %x, 8 ; 16-8
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%tmp1 = ashr exact i16 %tmp0, 8 ; 16-8
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%tmp2 = icmp eq i16 %tmp1, %x
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ret i1 %tmp2
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}
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define i1 @shifts_eqcmp_i32_i16(i32 %x) nounwind {
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; CHECK-LABEL: shifts_eqcmp_i32_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w0, sxth
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = shl i32 %x, 16 ; 32-16
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%tmp1 = ashr exact i32 %tmp0, 16 ; 32-16
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%tmp2 = icmp eq i32 %tmp1, %x
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ret i1 %tmp2
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}
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define i1 @shifts_eqcmp_i32_i8(i32 %x) nounwind {
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; CHECK-LABEL: shifts_eqcmp_i32_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w0, sxtb
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = shl i32 %x, 24 ; 32-8
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%tmp1 = ashr exact i32 %tmp0, 24 ; 32-8
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%tmp2 = icmp eq i32 %tmp1, %x
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ret i1 %tmp2
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}
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define i1 @shifts_eqcmp_i64_i32(i64 %x) nounwind {
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; CHECK-LABEL: shifts_eqcmp_i64_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, w0, sxtw
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = shl i64 %x, 32 ; 64-32
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%tmp1 = ashr exact i64 %tmp0, 32 ; 64-32
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%tmp2 = icmp eq i64 %tmp1, %x
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ret i1 %tmp2
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}
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define i1 @shifts_eqcmp_i64_i16(i64 %x) nounwind {
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; CHECK-LABEL: shifts_eqcmp_i64_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, w0, sxth
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = shl i64 %x, 48 ; 64-16
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%tmp1 = ashr exact i64 %tmp0, 48 ; 64-16
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%tmp2 = icmp eq i64 %tmp1, %x
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ret i1 %tmp2
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}
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define i1 @shifts_eqcmp_i64_i8(i64 %x) nounwind {
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; CHECK-LABEL: shifts_eqcmp_i64_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, w0, sxtb
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = shl i64 %x, 56 ; 64-8
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%tmp1 = ashr exact i64 %tmp0, 56 ; 64-8
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%tmp2 = icmp eq i64 %tmp1, %x
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ret i1 %tmp2
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}
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; ---------------------------------------------------------------------------- ;
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; add + icmp uge
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; ---------------------------------------------------------------------------- ;
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define i1 @add_ugecmp_i16_i8(i16 %x) nounwind {
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; CHECK-LABEL: add_ugecmp_i16_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: sub w8, w8, #128
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; CHECK-NEXT: lsr w8, w8, #8
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; CHECK-NEXT: cmp w8, #254
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; CHECK-NEXT: cset w0, hi
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, -128 ; ~0U << (8-1)
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%tmp1 = icmp uge i16 %tmp0, -256 ; ~0U << 8
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ret i1 %tmp1
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}
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define i1 @add_ugecmp_i32_i16_i8(i16 %xx) nounwind {
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; CHECK-LABEL: add_ugecmp_i32_i16_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: cmp w8, w8, sxtb
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%x = zext i16 %xx to i32
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%tmp0 = add i32 %x, -128 ; ~0U << (8-1)
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%tmp1 = icmp uge i32 %tmp0, -256 ; ~0U << 8
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ret i1 %tmp1
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}
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define i1 @add_ugecmp_i32_i16(i32 %x) nounwind {
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; CHECK-LABEL: add_ugecmp_i32_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w0, sxth
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i32 %x, -32768 ; ~0U << (16-1)
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%tmp1 = icmp uge i32 %tmp0, -65536 ; ~0U << 16
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ret i1 %tmp1
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}
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define i1 @add_ugecmp_i32_i8(i32 %x) nounwind {
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; CHECK-LABEL: add_ugecmp_i32_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w0, sxtb
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i32 %x, -128 ; ~0U << (8-1)
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%tmp1 = icmp uge i32 %tmp0, -256 ; ~0U << 8
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ret i1 %tmp1
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}
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define i1 @add_ugecmp_i64_i32(i64 %x) nounwind {
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; CHECK-LABEL: add_ugecmp_i64_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, w0, sxtw
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i64 %x, -2147483648 ; ~0U << (32-1)
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%tmp1 = icmp uge i64 %tmp0, -4294967296 ; ~0U << 32
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ret i1 %tmp1
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}
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define i1 @add_ugecmp_i64_i16(i64 %x) nounwind {
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; CHECK-LABEL: add_ugecmp_i64_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, w0, sxth
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i64 %x, -32768 ; ~0U << (16-1)
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%tmp1 = icmp uge i64 %tmp0, -65536 ; ~0U << 16
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ret i1 %tmp1
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}
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define i1 @add_ugecmp_i64_i8(i64 %x) nounwind {
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; CHECK-LABEL: add_ugecmp_i64_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, w0, sxtb
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i64 %x, -128 ; ~0U << (8-1)
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%tmp1 = icmp uge i64 %tmp0, -256 ; ~0U << 8
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ret i1 %tmp1
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}
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; Slightly more canonical variant
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define i1 @add_ugtcmp_i16_i8(i16 %x) nounwind {
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; CHECK-LABEL: add_ugtcmp_i16_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: sub w8, w8, #128
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; CHECK-NEXT: lsr w8, w8, #8
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; CHECK-NEXT: cmp w8, #254
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; CHECK-NEXT: cset w0, hi
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, -128 ; ~0U << (8-1)
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%tmp1 = icmp ugt i16 %tmp0, -257 ; ~0U << 8 - 1
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ret i1 %tmp1
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}
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; ---------------------------------------------------------------------------- ;
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; add + icmp ult
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; ---------------------------------------------------------------------------- ;
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define i1 @add_ultcmp_i16_i8(i16 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_i16_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w0
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; CHECK-NEXT: and w8, w8, #0xffff
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; CHECK-NEXT: cmp w8, w0, uxth
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, 128 ; 1U << (8-1)
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%tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8
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ret i1 %tmp1
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}
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define i1 @add_ultcmp_i32_i16(i32 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_i32_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w0, sxth
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i32 %x, 32768 ; 1U << (16-1)
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%tmp1 = icmp ult i32 %tmp0, 65536 ; 1U << 16
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ret i1 %tmp1
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}
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define i1 @add_ultcmp_i32_i8(i32 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_i32_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, w0, sxtb
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i32 %x, 128 ; 1U << (8-1)
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%tmp1 = icmp ult i32 %tmp0, 256 ; 1U << 8
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ret i1 %tmp1
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}
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define i1 @add_ultcmp_i64_i32(i64 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_i64_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, w0, sxtw
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i64 %x, 2147483648 ; 1U << (32-1)
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%tmp1 = icmp ult i64 %tmp0, 4294967296 ; 1U << 32
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ret i1 %tmp1
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}
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define i1 @add_ultcmp_i64_i16(i64 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_i64_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, w0, sxth
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i64 %x, 32768 ; 1U << (16-1)
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%tmp1 = icmp ult i64 %tmp0, 65536 ; 1U << 16
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ret i1 %tmp1
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}
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define i1 @add_ultcmp_i64_i8(i64 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_i64_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, w0, sxtb
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i64 %x, 128 ; 1U << (8-1)
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%tmp1 = icmp ult i64 %tmp0, 256 ; 1U << 8
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ret i1 %tmp1
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}
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; Slightly more canonical variant
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define i1 @add_ulecmp_i16_i8(i16 %x) nounwind {
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; CHECK-LABEL: add_ulecmp_i16_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w0
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; CHECK-NEXT: and w8, w8, #0xffff
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; CHECK-NEXT: cmp w8, w0, uxth
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, 128 ; 1U << (8-1)
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%tmp1 = icmp ule i16 %tmp0, 255 ; (1U << 8) - 1
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ret i1 %tmp1
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}
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; Negative tests
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; ---------------------------------------------------------------------------- ;
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; Adding not a constant
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define i1 @add_ultcmp_bad_i16_i8_add(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: add_ultcmp_bad_i16_i8_add:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, w1
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; CHECK-NEXT: and w8, w8, #0xffff
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; CHECK-NEXT: cmp w8, #256
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, %y
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%tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8
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ret i1 %tmp1
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}
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; Comparing not with a constant
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define i1 @add_ultcmp_bad_i16_i8_cmp(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: add_ultcmp_bad_i16_i8_cmp:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #128
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; CHECK-NEXT: and w8, w8, #0xffff
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; CHECK-NEXT: cmp w8, w1, uxth
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, 128 ; 1U << (8-1)
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%tmp1 = icmp ult i16 %tmp0, %y
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ret i1 %tmp1
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}
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; Second constant is not larger than the first one
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define i1 @add_ultcmp_bad_i8_i16(i16 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_bad_i8_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: add w8, w8, #128
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, 128 ; 1U << (8-1)
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%tmp1 = icmp ult i16 %tmp0, 128 ; 1U << (8-1)
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ret i1 %tmp1
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}
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; First constant is not power of two
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define i1 @add_ultcmp_bad_i16_i8_c0notpoweroftwo(i16 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_bad_i16_i8_c0notpoweroftwo:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #192
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; CHECK-NEXT: and w8, w8, #0xffff
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; CHECK-NEXT: cmp w8, #256
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, 192 ; (1U << (8-1)) + (1U << (8-1-1))
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%tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8
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ret i1 %tmp1
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}
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; Second constant is not power of two
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define i1 @add_ultcmp_bad_i16_i8_c1notpoweroftwo(i16 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_bad_i16_i8_c1notpoweroftwo:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #128
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; CHECK-NEXT: and w8, w8, #0xffff
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; CHECK-NEXT: cmp w8, #768
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, 128 ; 1U << (8-1)
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%tmp1 = icmp ult i16 %tmp0, 768 ; (1U << 8)) + (1U << (8+1))
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ret i1 %tmp1
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}
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; Magic check fails, 64 << 1 != 256
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define i1 @add_ultcmp_bad_i16_i8_magic(i16 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_bad_i16_i8_magic:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #64
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; CHECK-NEXT: and w8, w8, #0xffff
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; CHECK-NEXT: cmp w8, #256
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, 64 ; 1U << (8-1-1)
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%tmp1 = icmp ult i16 %tmp0, 256 ; 1U << 8
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ret i1 %tmp1
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}
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; Bad 'destination type'
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define i1 @add_ultcmp_bad_i16_i4(i16 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_bad_i16_i4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #8
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; CHECK-NEXT: and w8, w8, #0xffff
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; CHECK-NEXT: cmp w8, #16
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, 8 ; 1U << (4-1)
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%tmp1 = icmp ult i16 %tmp0, 16 ; 1U << 4
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ret i1 %tmp1
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}
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; Bad storage type
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define i1 @add_ultcmp_bad_i24_i8(i24 %x) nounwind {
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; CHECK-LABEL: add_ultcmp_bad_i24_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #128
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; CHECK-NEXT: and w8, w8, #0xffffff
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; CHECK-NEXT: cmp w8, #256
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%tmp0 = add i24 %x, 128 ; 1U << (8-1)
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%tmp1 = icmp ult i24 %tmp0, 256 ; 1U << 8
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ret i1 %tmp1
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}
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define i1 @add_ulecmp_bad_i16_i8(i16 %x) nounwind {
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; CHECK-LABEL: add_ulecmp_bad_i16_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, #1 // =0x1
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; CHECK-NEXT: ret
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%tmp0 = add i16 %x, 128 ; 1U << (8-1)
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%tmp1 = icmp ule i16 %tmp0, -1 ; when we +1 it, it will wrap to 0
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ret i1 %tmp1
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}
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