db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
124 lines
5.2 KiB
LLVM
124 lines
5.2 KiB
LLVM
; RUN: llc < %s -debug-only=legalize-types 2>&1 | FileCheck %s --check-prefix=CHECK-LEGALIZATION
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; RUN: llc < %s | FileCheck %s
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; REQUIRES: asserts
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target triple = "aarch64-unknown-linux-gnu"
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attributes #0 = {"target-features"="+sve" uwtable}
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declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64>, <8 x i64>, i64)
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declare <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double>, <8 x double>, i64)
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define <vscale x 2 x i64> @test_nxv2i64_v8i64(<vscale x 2 x i64> %a, <8 x i64> %b) #0 {
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; CHECK-LEGALIZATION: Legally typed node: [[T1:t[0-9]+]]: nxv2i64 = insert_subvector {{t[0-9]+}}, {{t[0-9]+}}, Constant:i64<0>
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; CHECK-LEGALIZATION: Legally typed node: [[T2:t[0-9]+]]: nxv2i64 = insert_subvector [[T1]], {{t[0-9]+}}, Constant:i64<2>
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; CHECK-LEGALIZATION: Legally typed node: [[T3:t[0-9]+]]: nxv2i64 = insert_subvector [[T2]], {{t[0-9]+}}, Constant:i64<4>
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; CHECK-LEGALIZATION: Legally typed node: [[T4:t[0-9]+]]: nxv2i64 = insert_subvector [[T3]], {{t[0-9]+}}, Constant:i64<6>
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; CHECK-LABEL: test_nxv2i64_v8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: addvl sp, sp, #-3
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
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; CHECK-NEXT: ptrue p1.d, vl2
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: mov w9, #2 // =0x2
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: sub x8, x8, #2
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: mov x10, sp
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; CHECK-NEXT: cmp x8, #2
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; CHECK-NEXT: csel x9, x8, x9, lo
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; CHECK-NEXT: cmp x8, #4
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; CHECK-NEXT: lsl x9, x9, #3
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; CHECK-NEXT: mov z0.d, p1/m, z1.d
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: str q2, [x10, x9]
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; CHECK-NEXT: mov w9, #4 // =0x4
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; CHECK-NEXT: addvl x10, sp, #1
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
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; CHECK-NEXT: csel x9, x8, x9, lo
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; CHECK-NEXT: cmp x8, #6
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; CHECK-NEXT: lsl x9, x9, #3
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; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: str q3, [x10, x9]
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; CHECK-NEXT: mov w9, #6 // =0x6
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #1, mul vl]
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; CHECK-NEXT: csel x8, x8, x9, lo
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; CHECK-NEXT: addvl x9, sp, #2
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; CHECK-NEXT: lsl x8, x8, #3
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; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl]
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; CHECK-NEXT: str q4, [x9, x8]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl]
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; CHECK-NEXT: addvl sp, sp, #3
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; CHECK-NEXT: .cfi_def_cfa wsp, 16
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: .cfi_restore w29
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; CHECK-NEXT: ret
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%r = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> %a, <8 x i64> %b, i64 0)
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ret <vscale x 2 x i64> %r
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}
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define <vscale x 2 x double> @test_nxv2f64_v8f64(<vscale x 2 x double> %a, <8 x double> %b) #0 {
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; CHECK-LEGALIZATION: Legally typed node: [[T1:t[0-9]+]]: nxv2f64 = insert_subvector {{t[0-9]+}}, {{t[0-9]+}}, Constant:i64<0>
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; CHECK-LEGALIZATION: Legally typed node: [[T2:t[0-9]+]]: nxv2f64 = insert_subvector [[T1]], {{t[0-9]+}}, Constant:i64<2>
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; CHECK-LEGALIZATION: Legally typed node: [[T3:t[0-9]+]]: nxv2f64 = insert_subvector [[T2]], {{t[0-9]+}}, Constant:i64<4>
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; CHECK-LEGALIZATION: Legally typed node: [[T4:t[0-9]+]]: nxv2f64 = insert_subvector [[T3]], {{t[0-9]+}}, Constant:i64<6>
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; CHECK-LABEL: test_nxv2f64_v8f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: addvl sp, sp, #-3
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
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; CHECK-NEXT: ptrue p1.d, vl2
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: mov w9, #2 // =0x2
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: sub x8, x8, #2
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: mov x10, sp
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; CHECK-NEXT: cmp x8, #2
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; CHECK-NEXT: csel x9, x8, x9, lo
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; CHECK-NEXT: cmp x8, #4
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; CHECK-NEXT: lsl x9, x9, #3
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; CHECK-NEXT: mov z0.d, p1/m, z1.d
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: str q2, [x10, x9]
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; CHECK-NEXT: mov w9, #4 // =0x4
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; CHECK-NEXT: addvl x10, sp, #1
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
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; CHECK-NEXT: csel x9, x8, x9, lo
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; CHECK-NEXT: cmp x8, #6
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; CHECK-NEXT: lsl x9, x9, #3
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; CHECK-NEXT: st1d { z0.d }, p0, [sp, #1, mul vl]
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; CHECK-NEXT: str q3, [x10, x9]
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; CHECK-NEXT: mov w9, #6 // =0x6
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #1, mul vl]
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; CHECK-NEXT: csel x8, x8, x9, lo
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; CHECK-NEXT: addvl x9, sp, #2
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; CHECK-NEXT: lsl x8, x8, #3
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; CHECK-NEXT: st1d { z0.d }, p0, [sp, #2, mul vl]
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; CHECK-NEXT: str q4, [x9, x8]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp, #2, mul vl]
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; CHECK-NEXT: addvl sp, sp, #3
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; CHECK-NEXT: .cfi_def_cfa wsp, 16
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: .cfi_restore w29
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; CHECK-NEXT: ret
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%r = call <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v8f64(<vscale x 2 x double> %a, <8 x double> %b, i64 0)
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ret <vscale x 2 x double> %r
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}
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