db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
174 lines
5.4 KiB
LLVM
174 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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declare i16 @llvm.sshl.sat.i16(i16, i16)
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declare <4 x i16> @llvm.sshl.sat.v4i16(<4 x i16>, <4 x i16>)
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; fold (shlsat undef, x) -> 0
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define i16 @combine_shl_undef(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 undef, i16 %y)
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ret i16 %tmp
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}
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; fold (shlsat x, undef) -> undef
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define i16 @combine_shl_by_undef(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_by_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 undef)
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ret i16 %tmp
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}
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; fold (shlsat poison, x) -> 0
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define i16 @combine_shl_poison(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_poison:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 poison, i16 %y)
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ret i16 %tmp
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}
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; fold (shlsat x, poison) -> undef
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define i16 @combine_shl_by_poison(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_by_poison:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 poison)
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ret i16 %tmp
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}
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; fold (shlsat x, bitwidth) -> undef
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define i16 @combine_shl_by_bitwidth(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_by_bitwidth:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 16)
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ret i16 %tmp
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}
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; fold (shlsat 0, x) -> 0
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define i16 @combine_shl_zero(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shl_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 0, i16 %y)
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ret i16 %tmp
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}
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; fold (shlsat x, 0) -> x
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define i16 @combine_shlsat_by_zero(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_by_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 %x, i16 0)
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ret i16 %tmp
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}
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; fold (shlsat c1, c2) -> c3
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define i16 @combine_shlsat_constfold(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_constfold:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, #32 // =0x20
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 8, i16 2)
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ret i16 %tmp
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}
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; fold (shlsat c1, c2) -> sat max
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define i16 @combine_shlsat_satmax(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_satmax:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, #32767 // =0x7fff
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 8, i16 15)
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ret i16 %tmp
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}
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; fold (shlsat c1, c2) -> sat min
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define i16 @combine_shlsat_satmin(i16 %x, i16 %y) nounwind {
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; CHECK-LABEL: combine_shlsat_satmin:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, #32768 // =0x8000
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; CHECK-NEXT: ret
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%tmp = call i16 @llvm.sshl.sat.i16(i16 -8, i16 15)
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ret i16 %tmp
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}
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declare void @sink4xi16(i16, i16, i16, i16)
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; fold (shlsat c1, c2) -> c3 , c1/c2/c3 being vectors
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define void @combine_shlsat_vector() nounwind {
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; CHECK-LABEL: combine_shlsat_vector:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: mov w0, #32 // =0x20
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; CHECK-NEXT: mov w1, #32767 // =0x7fff
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; CHECK-NEXT: mov w2, #65504 // =0xffe0
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; CHECK-NEXT: mov w3, #32768 // =0x8000
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; CHECK-NEXT: bl sink4xi16
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; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%tmp = call <4 x i16> @llvm.sshl.sat.v4i16(
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<4 x i16><i16 8, i16 8, i16 -8, i16 -8>,
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<4 x i16><i16 2, i16 15, i16 2, i16 15>)
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; Pass elements as arguments in a call to get CHECK statements that verify
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; the constant folding.
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%e0 = extractelement <4 x i16> %tmp, i16 0
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%e1 = extractelement <4 x i16> %tmp, i16 1
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%e2 = extractelement <4 x i16> %tmp, i16 2
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%e3 = extractelement <4 x i16> %tmp, i16 3
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call void @sink4xi16(i16 %e0, i16 %e1, i16 %e2, i16 %e3)
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ret void
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}
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; Fold shlsat -> shl, if known not to saturate.
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define i16 @combine_shlsat_to_shl(i16 %x) nounwind {
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; CHECK-LABEL: combine_shlsat_to_shl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w0, #0xfffffffc
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; CHECK-NEXT: ret
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%x2 = ashr i16 %x, 2
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%tmp = call i16 @llvm.sshl.sat.i16(i16 %x2, i16 2)
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ret i16 %tmp
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}
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; Do not fold shlsat -> shl.
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define i16 @combine_shlsat_to_shl_no_fold(i16 %x) nounwind {
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; CHECK-LABEL: combine_shlsat_to_shl_no_fold:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxth w8, w0
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; CHECK-NEXT: mov w9, #-65536 // =0xffff0000
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; CHECK-NEXT: mov w10, #-2147483648 // =0x80000000
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; CHECK-NEXT: ands w8, w9, w8, lsl #14
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; CHECK-NEXT: cinv w10, w10, ge
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; CHECK-NEXT: lsl w9, w8, #3
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; CHECK-NEXT: cmp w8, w9, asr #3
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; CHECK-NEXT: csel w8, w10, w9, ne
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; CHECK-NEXT: asr w0, w8, #16
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; CHECK-NEXT: ret
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%x2 = ashr i16 %x, 2
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%tmp = call i16 @llvm.sshl.sat.i16(i16 %x2, i16 3)
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ret i16 %tmp
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}
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; Fold shlsat -> shl, if known not to saturate.
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define <4 x i16> @combine_shlsat_to_shl_vec(<4 x i8> %a) nounwind {
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; CHECK-LABEL: combine_shlsat_to_shl_vec:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.4h, v0.4h, #8
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; CHECK-NEXT: sshr v0.4h, v0.4h, #8
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; CHECK-NEXT: shl v0.4h, v0.4h, #7
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; CHECK-NEXT: ret
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%sext = sext <4 x i8> %a to <4 x i16>
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%tmp = call <4 x i16> @llvm.sshl.sat.v4i16(
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<4 x i16> %sext,
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<4 x i16> <i16 7, i16 7, i16 7, i16 7>)
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ret <4 x i16> %tmp
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}
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