db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
125 lines
4.0 KiB
LLVM
125 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare <8 x i8> @llvm.cttz.v8i8(<8 x i8>, i1)
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declare <4 x i16> @llvm.cttz.v4i16(<4 x i16>, i1)
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declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1)
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declare <1 x i64> @llvm.cttz.v1i64(<1 x i64>, i1)
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declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1)
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declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1)
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declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)
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declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
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define <8 x i8> @cttz_v8i8(<8 x i8> %a) nounwind {
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; CHECK-LABEL: cttz_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.8b, #1
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; CHECK-NEXT: sub v1.8b, v0.8b, v1.8b
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; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
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; CHECK-NEXT: cnt v0.8b, v0.8b
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; CHECK-NEXT: ret
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%b = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %a, i1 true)
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ret <8 x i8> %b
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}
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define <4 x i16> @cttz_v4i16(<4 x i16> %a) nounwind {
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; CHECK-LABEL: cttz_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4h, #1
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; CHECK-NEXT: sub v1.4h, v0.4h, v1.4h
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; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
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; CHECK-NEXT: movi v1.4h, #16
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; CHECK-NEXT: clz v0.4h, v0.4h
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; CHECK-NEXT: sub v0.4h, v1.4h, v0.4h
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; CHECK-NEXT: ret
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%b = call <4 x i16> @llvm.cttz.v4i16(<4 x i16> %a, i1 true)
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ret <4 x i16> %b
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}
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define <2 x i32> @cttz_v2i32(<2 x i32> %a) nounwind {
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; CHECK-LABEL: cttz_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.2s, #1
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; CHECK-NEXT: sub v1.2s, v0.2s, v1.2s
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; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
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; CHECK-NEXT: movi v1.2s, #32
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; CHECK-NEXT: clz v0.2s, v0.2s
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; CHECK-NEXT: sub v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: ret
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%b = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 true)
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ret <2 x i32> %b
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}
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define <1 x i64> @cttz_v1i64(<1 x i64> %a) nounwind {
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; CHECK-LABEL: cttz_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: sub d1, d0, d1
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; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
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; CHECK-NEXT: cnt v0.8b, v0.8b
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; CHECK-NEXT: uaddlp v0.4h, v0.8b
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; CHECK-NEXT: uaddlp v0.2s, v0.4h
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; CHECK-NEXT: uaddlp v0.1d, v0.2s
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; CHECK-NEXT: ret
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%b = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %a, i1 true)
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ret <1 x i64> %b
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}
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define <16 x i8> @cttz_v16i8(<16 x i8> %a) nounwind {
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; CHECK-LABEL: cttz_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.16b, #1
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; CHECK-NEXT: sub v1.16b, v0.16b, v1.16b
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: cnt v0.16b, v0.16b
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; CHECK-NEXT: ret
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%b = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 true)
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ret <16 x i8> %b
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}
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define <8 x i16> @cttz_v8i16(<8 x i16> %a) nounwind {
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; CHECK-LABEL: cttz_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.8h, #1
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; CHECK-NEXT: sub v1.8h, v0.8h, v1.8h
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: movi v1.8h, #16
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; CHECK-NEXT: clz v0.8h, v0.8h
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; CHECK-NEXT: sub v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: ret
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%b = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 true)
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ret <8 x i16> %b
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}
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define <4 x i32> @cttz_v4i32(<4 x i32> %a) nounwind {
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; CHECK-LABEL: cttz_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: sub v1.4s, v0.4s, v1.4s
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: movi v1.4s, #32
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; CHECK-NEXT: clz v0.4s, v0.4s
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; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ret
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%b = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 true)
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ret <4 x i32> %b
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}
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define <2 x i64> @cttz_v2i64(<2 x i64> %a) nounwind {
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; CHECK-LABEL: cttz_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: sub v1.2d, v0.2d, v1.2d
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: cnt v0.16b, v0.16b
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; CHECK-NEXT: uaddlp v0.8h, v0.16b
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; CHECK-NEXT: uaddlp v0.4s, v0.8h
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; CHECK-NEXT: uaddlp v0.2d, v0.4s
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; CHECK-NEXT: ret
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%b = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)
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ret <2 x i64> %b
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}
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