7d8fd4f5db
Another issue unearthed by D127115 We take a long time to canonicalize an insert_vector_elt chain before being able to convert it into a build_vector - even if they are already in ascending insertion order, we fold the nodes one at a time into the build_vector 'seed', leaving plenty of time for other folds to alter it (in particular recognising when they come from extract_vector_elt resulting in a shuffle_vector that is much harder to fold with). D127115 makes this particularly difficult as we're almost guaranteed to have the lost the sequence before all possible insertions have been folded. This patch proposes to begin at the last insertion and attempt to collect all the (oneuse) insertions right away and create the build_vector before its too late. Differential Revision: https://reviews.llvm.org/D127595
34 lines
1.3 KiB
LLVM
34 lines
1.3 KiB
LLVM
; REQUIRES: arm-registered-target
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; REQUIRES: asserts
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; RUN: llc -o /dev/null %s -debug-only=legalize-types 2>&1 | FileCheck %s
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; This test check that when v4f64 gets broken down to two v2f64 it maintains
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; the "nnan" flags.
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; CHECK: Legalizing node: [[VFOUR:t.*]]: v4f64 = BUILD_VECTOR
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; CHECK-NEXT: Analyzing result type: v4f64
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; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR
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; CHECK: Legalizing node: [[VTWOA:t.*]]: v2f64 = BUILD_VECTOR
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; CHECK: Legally typed node: [[VTWOA]]: v2f64 = BUILD_VECTOR
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; CHECK: Legalizing node: [[VTWOB:t.*]]: v2f64 = BUILD_VECTOR
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; CHECK: Legally typed node: [[VTWOB]]: v2f64 = BUILD_VECTOR
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; CHECK: Legalizing node: t30: v2f64 = fmaxnum nnan reassoc [[VTWOB]], [[VTWOA]]
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--linux-gnu"
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; Function Attrs: norecurse nounwind
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define fastcc double @test(double %a0, double %a1, double %a2, double %a3) unnamed_addr #1 {
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entry:
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%0 = insertelement <4 x double> undef, double %a0, i32 0
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%1 = insertelement <4 x double> %0, double %a1, i32 1
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%2 = insertelement <4 x double> %1, double %a2, i32 2
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%3 = insertelement <4 x double> %2, double %a3, i32 3
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%4 = call nnan reassoc double @llvm.vector.reduce.fmax.v4f64(<4 x double> %3)
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ret double %4
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}
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declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)
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