db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
27 lines
894 B
LLVM
27 lines
894 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64_32-apple-watchos2.0.0 --aarch64-neon-syntax=generic | FileCheck %s
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target datalayout = "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128"
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target triple = "arm64_32-apple-watchos2.0.0"
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; CHECK-LABEL: lCPI0_0:
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; CHECK-NEXT: .quad 36
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; CHECK-NEXT: .quad 4804
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define <2 x ptr> @vector_gep(<2 x ptr> %0) {
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; CHECK-LABEL: vector_gep:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: Lloh0:
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; CHECK-NEXT: adrp x8, lCPI0_0@PAGE
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; CHECK-NEXT: Lloh1:
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; CHECK-NEXT: ldr q1, [x8, lCPI0_0@PAGEOFF]
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; CHECK-NEXT: add v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
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entry:
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%1 = getelementptr i8, <2 x ptr> %0, <2 x i32> <i32 36, i32 4804>
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ret <2 x ptr> %1
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}
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