e39f6c1844
There are many tests that specify a target triple/CPU flags but no DataLayout which can lead to IR being generated that has unusual behaviour. This commit attempts to use the default DataLayout based on the relevant flags if there is no explicit override on the command line or in the IR file. One thing that is not currently possible to differentiate from a missing datalayout `target datalayout = ""` in the IR file since the current APIs don't allow detecting this case. If it is considered useful to support this case (instead of passing "-data-layout=" on the command line), I can change IR parsers to track whether they have seen such a directive and change the callback type. Differential Revision: https://reviews.llvm.org/D141060
75 lines
3.1 KiB
LLVM
75 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-simplifylib < %s | FileCheck %s
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; private variant of sincos is defined but marked nobuiltin, so
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; introduce a call to the generic one.
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define float @_Z3sinf(float %x) {
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; CHECK-LABEL: define float @_Z3sinf
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; CHECK-SAME: (float [[X:%.*]]) {
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; CHECK-NEXT: [[RESULT:%.*]] = call float asm "
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; CHECK-NEXT: ret float [[RESULT]]
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;
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%result = call float asm "; $0 = sin($1)","=v,v"(float %x)
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ret float %result
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}
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define float @_Z3cosf(float %x) {
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; CHECK-LABEL: define float @_Z3cosf
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; CHECK-SAME: (float [[X:%.*]]) {
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; CHECK-NEXT: [[RESULT:%.*]] = call float asm "
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; CHECK-NEXT: ret float [[RESULT]]
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;
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%result = call float asm "; $0 = cos($1)","=v,v"(float %x)
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ret float %result
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}
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define float @_Z6sincosfPU3AS5f(float %x, ptr addrspace(5) %ptr) nobuiltin {
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; CHECK-LABEL: define float @_Z6sincosfPU3AS5f
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; CHECK-SAME: (float [[X:%.*]], ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[RESULT0:%.*]] = call float asm "
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; CHECK-NEXT: [[RESULT1:%.*]] = call float asm "
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; CHECK-NEXT: store float [[RESULT1]], ptr addrspace(5) [[PTR]], align 4
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; CHECK-NEXT: ret float [[RESULT0]]
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;
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%result0 = call float asm "; $0 = sin($1)","=v,v"(float %x)
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%result1 = call float asm "; $0 = cos($1)","=v,v"(float %x)
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store float %result1, ptr addrspace(5) %ptr
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ret float %result0
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}
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define float @_Z6sincosfPU3AS0f(float %x, ptr %ptr) {
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; CHECK-LABEL: define float @_Z6sincosfPU3AS0f
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; CHECK-SAME: (float [[X:%.*]], ptr [[PTR:%.*]]) {
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; CHECK-NEXT: [[RESULT0:%.*]] = call float asm "
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; CHECK-NEXT: [[RESULT1:%.*]] = call float asm "
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; CHECK-NEXT: store float [[RESULT1]], ptr [[PTR]], align 4
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; CHECK-NEXT: ret float [[RESULT0]]
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;
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%result0 = call float asm "; $0 = sin($1)","=v,v"(float %x)
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%result1 = call float asm "; $0 = cos($1)","=v,v"(float %x)
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store float %result1, ptr %ptr
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ret float %result0
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}
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define void @sincos_f32(float %x, ptr addrspace(1) nocapture writeonly %sin_out, ptr addrspace(1) nocapture writeonly %cos_out) {
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; CHECK-LABEL: define void @sincos_f32
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; CHECK-SAME: (float [[X:%.*]], ptr addrspace(1) nocapture writeonly [[SIN_OUT:%.*]], ptr addrspace(1) nocapture writeonly [[COS_OUT:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[__SINCOS_:%.*]] = alloca float, align 4, addrspace(5)
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; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(5) [[__SINCOS_]] to ptr
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; CHECK-NEXT: [[TMP1:%.*]] = call contract float @_Z6sincosfPU3AS0f(float [[X]], ptr [[TMP0]])
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; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr addrspace(5) [[__SINCOS_]], align 4
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; CHECK-NEXT: store float [[TMP1]], ptr addrspace(1) [[SIN_OUT]], align 4
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; CHECK-NEXT: [[CALL1:%.*]] = tail call contract float @_Z3cosf(float [[X]])
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; CHECK-NEXT: store float [[TMP2]], ptr addrspace(1) [[COS_OUT]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%call = tail call contract float @_Z3sinf(float %x)
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store float %call, ptr addrspace(1) %sin_out, align 4
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%call1 = tail call contract float @_Z3cosf(float %x)
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store float %call1, ptr addrspace(1) %cos_out, align 4
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ret void
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}
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