9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
159 lines
5.5 KiB
LLVM
159 lines
5.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-NOHSA,GCN-NOHSA,FUNC %s
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; RUN: llc -global-isel -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-NOHSA,GCN-NOHSA,FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=VI-NOHSA,GCN-NOHSA,FUNC %s
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=VI-NOHSA,GCN-NOHSA,FUNC %s
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; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
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; Legacy intrinsics that just read implicit parameters
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; FUNC-LABEL: {{^}}ngroups_x:
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[0].X
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define amdgpu_kernel void @ngroups_x (ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.x() #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}ngroups_y:
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y
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define amdgpu_kernel void @ngroups_y (ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.y() #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}ngroups_z:
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z
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define amdgpu_kernel void @ngroups_z (ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.z() #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_size_x:
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[0].W
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define amdgpu_kernel void @global_size_x (ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.x() #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_size_y:
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[1].X
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define amdgpu_kernel void @global_size_y (ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.y() #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}global_size_z:
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[1].Y
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define amdgpu_kernel void @global_size_z (ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.z() #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_x:
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[1].Z
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define amdgpu_kernel void @local_size_x (ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.x() #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_y:
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[1].W
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define amdgpu_kernel void @local_size_y (ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.y() #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_z:
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[2].X
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define amdgpu_kernel void @local_size_z (ptr addrspace(1) %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.z() #0
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.r600.read.ngroups.x() #0
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declare i32 @llvm.r600.read.ngroups.y() #0
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declare i32 @llvm.r600.read.ngroups.z() #0
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declare i32 @llvm.r600.read.global.size.x() #0
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declare i32 @llvm.r600.read.global.size.y() #0
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declare i32 @llvm.r600.read.global.size.z() #0
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declare i32 @llvm.r600.read.local.size.x() #0
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declare i32 @llvm.r600.read.local.size.y() #0
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declare i32 @llvm.r600.read.local.size.z() #0
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attributes #0 = { readnone }
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