9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
79 lines
2.1 KiB
LLVM
79 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}s_clear_msb:
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; SI: s_bitset0_b32 s{{[0-9]+}}, 31
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define amdgpu_kernel void @s_clear_msb(ptr addrspace(1) %out, i32 %in) {
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%x = and i32 %in, 2147483647
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}s_set_msb:
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; SI: s_bitset1_b32 s{{[0-9]+}}, 31
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define amdgpu_kernel void @s_set_msb(ptr addrspace(1) %out, i32 %in) {
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%x = or i32 %in, 2147483648
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}s_clear_lsb:
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, -2
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define amdgpu_kernel void @s_clear_lsb(ptr addrspace(1) %out, i32 %in) {
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%x = and i32 %in, 4294967294
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}s_set_lsb:
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
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define amdgpu_kernel void @s_set_lsb(ptr addrspace(1) %out, i32 %in) {
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%x = or i32 %in, 1
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}s_clear_midbit:
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; SI: s_bitset0_b32 s{{[0-9]+}}, 8
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define amdgpu_kernel void @s_clear_midbit(ptr addrspace(1) %out, i32 %in) {
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%x = and i32 %in, 4294967039
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}s_set_midbit:
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; SI: s_bitset1_b32 s{{[0-9]+}}, 8
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define amdgpu_kernel void @s_set_midbit(ptr addrspace(1) %out, i32 %in) {
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%x = or i32 %in, 256
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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@gv = external addrspace(1) global i32
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; Make sure there's no verifier error with an undef source.
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; SI-LABEL: {{^}}bitset_verifier_error:
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; SI-NOT: %bb.1:
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
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define void @bitset_verifier_error() local_unnamed_addr #0 {
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bb:
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%i = call float @llvm.fabs.f32(float undef) #0
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%i1 = bitcast float %i to i32
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store i32 %i1, ptr addrspace(1) @gv
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br label %bb2
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bb2:
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%i3 = call float @llvm.fabs.f32(float undef) #0
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%i4 = fcmp fast ult float %i3, 0x3FEFF7CEE0000000
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br i1 %i4, label %bb5, label %bb6
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bb5:
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unreachable
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bb6:
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unreachable
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}
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declare float @llvm.fabs.f32(float) #0
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attributes #0 = { nounwind readnone speculatable willreturn }
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