af6ff98c53
Move SIPreAllocateWWMRegs pass to just before VGPR allocation. This saves recomputation of the virtual matrix and live reg map, with the slight regression in O0 that live intervals and slot indexes must be computed.
92 lines
6.1 KiB
LLVM
92 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -O0 -verify-machineinstrs --stop-after=regallocfast,1 -o - %s | FileCheck -check-prefix=REGALLOC %s
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; Test to check if the bb prolog spills are inserted correctly during regalloc.
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define i32 @prolog_spill(i32 %arg0, i32 %arg1, i32 %arg2) {
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; REGALLOC-LABEL: name: prolog_spill
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; REGALLOC: bb.0.bb.0:
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; REGALLOC-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
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; REGALLOC-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
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; REGALLOC-NEXT: {{ $}}
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; REGALLOC-NEXT: renamable $vgpr3 = IMPLICIT_DEF
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; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr2, %stack.5, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5)
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; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.4, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5)
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; REGALLOC-NEXT: renamable $vgpr1 = COPY $vgpr0
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; REGALLOC-NEXT: $vgpr0 = SI_SPILL_WWM_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
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; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 49
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; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = V_CMP_GT_I32_e64 killed $vgpr1, killed $sgpr4, implicit $exec
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; REGALLOC-NEXT: renamable $sgpr6 = IMPLICIT_DEF
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; REGALLOC-NEXT: renamable $vgpr1 = COPY killed renamable $sgpr6
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; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
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; REGALLOC-NEXT: renamable $sgpr6_sgpr7 = COPY $exec, implicit-def $exec
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; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 renamable $sgpr6_sgpr7, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
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; REGALLOC-NEXT: renamable $sgpr6_sgpr7 = S_XOR_B64 renamable $sgpr4_sgpr5, killed renamable $sgpr6_sgpr7, implicit-def dead $scc
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; REGALLOC-NEXT: renamable $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr6, 0, $vgpr0, implicit-def $sgpr6_sgpr7, implicit $sgpr6_sgpr7
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; REGALLOC-NEXT: renamable $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr7, 1, $vgpr0, implicit killed $sgpr6_sgpr7
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; REGALLOC-NEXT: SI_SPILL_WWM_V32_SAVE killed $vgpr0, %stack.2, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
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; REGALLOC-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr4_sgpr5
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; REGALLOC-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
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; REGALLOC-NEXT: S_BRANCH %bb.3
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; REGALLOC-NEXT: {{ $}}
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; REGALLOC-NEXT: bb.1.Flow:
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; REGALLOC-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
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; REGALLOC-NEXT: {{ $}}
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; REGALLOC-NEXT: $vgpr0 = SI_SPILL_WWM_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
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; REGALLOC-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr4_sgpr5
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; REGALLOC-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1
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; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 killed renamable $sgpr4_sgpr5, implicit-def $exec, implicit-def dead $scc, implicit $exec
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; REGALLOC-NEXT: $vgpr1 = SI_SPILL_V32_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
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; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
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; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
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; REGALLOC-NEXT: renamable $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr4, 2, $vgpr0, implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5
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; REGALLOC-NEXT: renamable $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr5, 3, $vgpr0, implicit $sgpr4_sgpr5
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; REGALLOC-NEXT: SI_SPILL_WWM_V32_SAVE killed $vgpr0, %stack.2, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5)
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; REGALLOC-NEXT: $exec = S_XOR_B64_term $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
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; REGALLOC-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
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; REGALLOC-NEXT: S_BRANCH %bb.2
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; REGALLOC-NEXT: {{ $}}
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; REGALLOC-NEXT: bb.2.bb.1:
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; REGALLOC-NEXT: successors: %bb.4(0x80000000)
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; REGALLOC-NEXT: {{ $}}
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; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
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; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 10
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; REGALLOC-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, killed $sgpr4, 0, implicit $exec
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; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5)
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; REGALLOC-NEXT: S_BRANCH %bb.4
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; REGALLOC-NEXT: {{ $}}
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; REGALLOC-NEXT: bb.3.bb.2:
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; REGALLOC-NEXT: successors: %bb.1(0x80000000)
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; REGALLOC-NEXT: {{ $}}
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; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.5, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5)
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; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 20
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; REGALLOC-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, killed $sgpr4, 0, implicit $exec
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; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5)
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; REGALLOC-NEXT: S_BRANCH %bb.1
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; REGALLOC-NEXT: {{ $}}
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; REGALLOC-NEXT: bb.4.bb.3:
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; REGALLOC-NEXT: $vgpr1 = SI_SPILL_WWM_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
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; REGALLOC-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr1, 2, implicit-def $sgpr4_sgpr5
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; REGALLOC-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR $vgpr1, 3
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; REGALLOC-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
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; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.6, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5)
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; REGALLOC-NEXT: renamable $vgpr0 = V_LSHL_ADD_U32_e64 killed $vgpr0, 2, $vgpr0, implicit $exec
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; REGALLOC-NEXT: KILL killed renamable $vgpr1
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; REGALLOC-NEXT: SI_RETURN implicit killed $vgpr0
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bb.0:
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%cmp = icmp slt i32 %arg0, 50
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br i1 %cmp, label %bb.1, label %bb.2
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bb.1:
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%val1 = add i32 %arg1, 10
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br label %bb.3
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bb.2:
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%val2 = add i32 %arg2, 20
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br label %bb.3
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bb.3:
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%val = phi i32 [ %val1, %bb.1 ], [ %val2, %bb.2 ]
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%ret = mul i32 %val, 5;
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ret i32 %ret
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}
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