9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
42 lines
1.5 KiB
LLVM
42 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
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; This used to crash because during intermediate control flow lowering, there
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; was a sequence
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; s_mov_b64 s[0:1], exec
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; s_and_b64 s[2:3], s[0:1], s[2:3] ; def & use of the same register pair
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; ...
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; s_mov_b64_term exec, s[2:3]
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; that was not treated correctly.
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;
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; GCN-LABEL: {{^}}ham:
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; GCN-DAG: v_cmp_lt_f32_e64 [[OTHERCC:s\[[0-9]+:[0-9]+\]]],
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; GCN-DAG: v_cmp_lt_f32_e32 vcc,
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; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]]
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; GCN: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[AND]]
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; GCN-NEXT: s_cbranch_execz .LBB0_{{[0-9]+}}
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; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %bb4
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; GCN: ds_write_b32
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; GCN: .LBB0_{{[0-9]+}}: ; %UnifiedReturnBlock
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; GCN-NEXT: s_endpgm
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; GCN-NEXT: .Lfunc_end
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define amdgpu_ps void @ham(float %arg, float %arg1) #0 {
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bb:
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%tmp = fcmp ogt float %arg, 0.000000e+00
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%tmp2 = fcmp ogt float %arg1, 0.000000e+00
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%tmp3 = and i1 %tmp, %tmp2
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br i1 %tmp3, label %bb4, label %bb5
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bb4: ; preds = %bb
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store volatile i32 4, ptr addrspace(3) undef
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unreachable
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bb5: ; preds = %bb
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ret void
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}
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attributes #0 = { nounwind readonly "InitialPSInputAddr"="36983" }
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attributes #1 = { nounwind readnone }
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