9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
72 lines
2.6 KiB
LLVM
72 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s
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; GCN-LABEL: name: s_abs_i32
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; GCN: S_ABS_I32
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define amdgpu_kernel void @s_abs_i32(ptr addrspace(1) %out, i32 %val) nounwind {
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%neg = sub i32 0, %val
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%cond = icmp sgt i32 %val, %neg
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%res = select i1 %cond, i32 %val, i32 %neg
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%res2 = add i32 %res, 2
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store i32 %res2, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: v_abs_i32
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; SI: V_SUB_CO_U32_e64
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; GFX900: V_SUB_U32_e64
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; GCN: V_MAX_I32_e64
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define amdgpu_kernel void @v_abs_i32(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds i32, ptr addrspace(1) %src, i32 %tid
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%val = load i32, ptr addrspace(1) %gep.in, align 4
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%neg = sub i32 0, %val
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%cond = icmp sgt i32 %val, %neg
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%res = select i1 %cond, i32 %val, i32 %neg
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%res2 = add i32 %res, 2
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store i32 %res2, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: s_abs_v2i32
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; GCN: S_ABS_I32
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; GCN: S_ABS_I32
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define amdgpu_kernel void @s_abs_v2i32(ptr addrspace(1) %out, <2 x i32> %val) nounwind {
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%z0 = insertelement <2 x i32> undef, i32 0, i32 0
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%z1 = insertelement <2 x i32> %z0, i32 0, i32 1
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%t0 = insertelement <2 x i32> undef, i32 2, i32 0
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%t1 = insertelement <2 x i32> %t0, i32 2, i32 1
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%neg = sub <2 x i32> %z1, %val
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%cond = icmp sgt <2 x i32> %val, %neg
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%res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg
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%res2 = add <2 x i32> %res, %t1
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store <2 x i32> %res2, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: v_abs_v2i32
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; SI: V_SUB_CO_U32_e64
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; GFX900: V_SUB_U32_e64
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; GCN: V_MAX_I32_e64
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; GCN: V_MAX_I32_e64
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define amdgpu_kernel void @v_abs_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {
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%z0 = insertelement <2 x i32> undef, i32 0, i32 0
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%z1 = insertelement <2 x i32> %z0, i32 0, i32 1
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%t0 = insertelement <2 x i32> undef, i32 2, i32 0
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%t1 = insertelement <2 x i32> %t0, i32 2, i32 1
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds <2 x i32>, ptr addrspace(1) %src, i32 %tid
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%val = load <2 x i32>, ptr addrspace(1) %gep.in, align 4
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%neg = sub <2 x i32> %z1, %val
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%cond = icmp sgt <2 x i32> %val, %neg
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%res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg
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%res2 = add <2 x i32> %res, %t1
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store <2 x i32> %res2, ptr addrspace(1) %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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