9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
44 lines
1.4 KiB
LLVM
44 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: name: uniform_bitreverse_i32
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; GCN: S_BREV_B32
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define amdgpu_kernel void @uniform_bitreverse_i32(i32 %val, ptr addrspace(1) %out) {
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%res = call i32 @llvm.bitreverse.i32(i32 %val)
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: divergent_bitreverse_i32
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; GCN: V_BFREV_B32
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define amdgpu_kernel void @divergent_bitreverse_i32(i32 %val, ptr addrspace(1) %out) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%divergent = add i32 %val, %tid
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%res = call i32 @llvm.bitreverse.i32(i32 %divergent)
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: uniform_bitreverse_i64
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; GCN: S_BREV_B64
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define amdgpu_kernel void @uniform_bitreverse_i64(i64 %val, ptr addrspace(1) %out) {
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%res = call i64 @llvm.bitreverse.i64(i64 %val)
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store i64 %res, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: divergent_bitreverse_i64
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; GCN: V_BFREV_B32
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; GCN: V_BFREV_B32
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define amdgpu_kernel void @divergent_bitreverse_i64(i64 %val, ptr addrspace(1) %out) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%ext = zext i32 %tid to i64
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%divergent = add i64 %val, %ext
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%res = call i64 @llvm.bitreverse.i64(i64 %divergent)
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store i64 %res, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i32 @llvm.bitreverse.i32(i32)
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declare i64 @llvm.bitreverse.i64(i64)
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