9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
65 lines
2.5 KiB
LLVM
65 lines
2.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: name: s_ctlz_i32
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; GCN: S_FLBIT_I32_B32
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define amdgpu_kernel void @s_ctlz_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {
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%ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone
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store i32 %ctlz, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: v_ctlz_i32
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; GCN: V_FFBH_U32_e64
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define amdgpu_kernel void @v_ctlz_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid
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%val = load i32, ptr addrspace(1) %in.gep, align 4
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%ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone
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store i32 %ctlz, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: s_cttz_i32
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; GCN: S_FF1_I32_B32
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define amdgpu_kernel void @s_cttz_i32(ptr addrspace(1) noalias %out, i32 %val) nounwind {
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%cttz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone
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store i32 %cttz, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: v_cttz_i32
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; GCN: V_FFBL_B32_e64
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define amdgpu_kernel void @v_cttz_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid
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%val = load i32, ptr addrspace(1) %in.gep, align 4
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%cttz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone
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store i32 %cttz, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: s_flbit
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; GCN: S_FLBIT_I32
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define amdgpu_kernel void @s_flbit(ptr addrspace(1) noalias %out, i32 %val) #0 {
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%r = call i32 @llvm.amdgcn.sffbh.i32(i32 %val)
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store i32 %r, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: name: v_flbit
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; GCN: V_FFBH_I32_e64
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define amdgpu_kernel void @v_flbit(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %valptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i32, ptr addrspace(1) %valptr, i32 %tid
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%val = load i32, ptr addrspace(1) %in.gep, align 4
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%r = call i32 @llvm.amdgcn.sffbh.i32(i32 %val)
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store i32 %r, ptr addrspace(1) %out, align 4
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ret void
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}
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declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
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declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
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declare i32 @llvm.amdgcn.sffbh.i32(i32)
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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