9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
96 lines
3.4 KiB
LLVM
96 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope --check-prefixes=GCN %s
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define amdgpu_kernel void @uniform_sext_in_reg_i8_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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; GCN-LABEL: uniform_sext_in_reg_i8_to_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_add_i32 s2, s2, s3
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; GCN-NEXT: s_sext_i32_i8 s2, s2
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_mov_b32 s4, s0
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; GCN-NEXT: s_mov_b32 s5, s1
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; GCN-NEXT: v_mov_b32_e32 v0, s2
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; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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%c = add i32 %a, %b ; add to prevent folding into extload
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%shl = shl i32 %c, 24
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%ashr = ashr i32 %shl, 24
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store i32 %ashr, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @divergent_sext_in_reg_i8_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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; GCN-LABEL: divergent_sext_in_reg_i8_to_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s4, s0
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; GCN-NEXT: s_mov_b32 s5, s1
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; GCN-NEXT: s_add_i32 s0, s2, s3
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 8
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; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%c = add i32 %a, %b ; add to prevent folding into extload
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%c.divergent = add i32 %c, %tid
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%shl = shl i32 %c.divergent, 24
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%ashr = ashr i32 %shl, 24
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store i32 %ashr, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @uniform_sext_in_reg_i16_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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; GCN-LABEL: uniform_sext_in_reg_i16_to_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_add_i32 s2, s2, s3
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; GCN-NEXT: s_sext_i32_i16 s2, s2
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_mov_b32 s4, s0
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; GCN-NEXT: s_mov_b32 s5, s1
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; GCN-NEXT: v_mov_b32_e32 v0, s2
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; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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%c = add i32 %a, %b ; add to prevent folding into extload
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%shl = shl i32 %c, 16
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%ashr = ashr i32 %shl, 16
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store i32 %ashr, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @divergent_sext_in_reg_i16_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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; GCN-LABEL: divergent_sext_in_reg_i16_to_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s4, s0
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; GCN-NEXT: s_mov_b32 s5, s1
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; GCN-NEXT: s_add_i32 s0, s2, s3
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%c = add i32 %a, %b ; add to prevent folding into extload
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%c.divergent = add i32 %c, %tid
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%shl = shl i32 %c.divergent, 16
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%ashr = ashr i32 %shl, 16
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store i32 %ashr, ptr addrspace(1) %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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