9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
45 lines
1.3 KiB
LLVM
45 lines
1.3 KiB
LLVM
; RUN: llc -mtriple=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN_DL %s
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; GCN-LABEL: name: uniform_xnor_i64
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; GCN: S_XNOR_B64
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define amdgpu_kernel void @uniform_xnor_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {
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%xor = xor i64 %a, %b
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%res = xor i64 %xor, -1
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store i64 %res, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: divergent_xnor_i64
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; GCN: V_XOR_B32_e64
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; GCN: V_XOR_B32_e64
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; GCN: V_NOT_B32_e32
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; GCN: V_NOT_B32_e32
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; GCN_DL: V_XNOR_B32_e64
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; GCN_DL: V_XNOR_B32_e64
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define i64 @divergent_xnor_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {
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%xor = xor i64 %a, %b
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%res = xor i64 %xor, -1
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ret i64 %res
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}
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; GCN-LABEL: name: uniform_xnor_i32
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; GCN: S_XNOR_B32
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define amdgpu_kernel void @uniform_xnor_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
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%xor = xor i32 %a, %b
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%res = xor i32 %xor, -1
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store i32 %res, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: divergent_xnor_i32
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; GCN: V_XOR_B32_e64
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; GCN: V_NOT_B32_e32
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; GCN_DL: V_XNOR_B32_e64
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define i32 @divergent_xnor_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
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%xor = xor i32 %a, %b
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%res = xor i32 %xor, -1
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ret i32 %res
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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