9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
113 lines
3.7 KiB
LLVM
113 lines
3.7 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -stress-early-ifcvt -amdgpu-early-ifcvt=1 -mtriple=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCNX3 %s
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; FIXME: Most of these cases that don't trigger because of broken cost
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; heuristics. Should not need -stress-early-ifcvt
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle64:
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; GCN: buffer_load_dwordx2 v[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]]
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; GCN: v_cmp_neq_f64_e32 vcc, 1.0, v[[[VAL_LO]]:[[VAL_HI]]]
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; GCN: v_add_f64 v[[[ADD_LO:[0-9]+]]:[[ADD_HI:[0-9]+]]], v[[[VAL_LO]]:[[VAL_HI]]], v[[[VAL_LO]]:[[VAL_HI]]]
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; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_LO:[0-9]+]], v[[ADD_LO]], v[[VAL_LO]], vcc
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; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_HI:[0-9]+]], v[[ADD_HI]], v[[VAL_HI]], vcc
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; GCN: buffer_store_dwordx2 v[[[RESULT_LO]]:[[RESULT_HI]]]
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
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entry:
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%v = load double, ptr addrspace(1) %in
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%cc = fcmp oeq double %v, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = fadd double %v, %v
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br label %endif
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endif:
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%r = phi double [ %v, %entry ], [ %u, %if ]
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store double %r, ptr addrspace(1) %out
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ret void
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}
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; vcc branch with SGPR inputs
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; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle64:
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; GCN: v_cmp_neq_f64
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; GCN: v_add_f64
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; GCN: v_cndmask_b32_e32
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; GCN: v_cndmask_b32_e32
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define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
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entry:
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%v = load double, ptr addrspace(4) %in
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%cc = fcmp oeq double %v, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = fadd double %v, %v
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br label %endif
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endif:
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%r = phi double [ %v, %entry ], [ %u, %if ]
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store double %r, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle96:
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; GCN: v_cmp_neq_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.0
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: s_mov_b64 vcc, [[CMP]]
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; SI-DAG: buffer_store_dwordx2
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; SI-DAG: buffer_store_dword v
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; GCNX3: buffer_store_dwordx3
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle96(ptr addrspace(1) %out, ptr addrspace(1) %in, float %cnd) #0 {
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entry:
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%v = load <3 x i32>, ptr addrspace(1) %in
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%cc = fcmp oeq float %cnd, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = add <3 x i32> %v, %v
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br label %endif
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endif:
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%r = phi <3 x i32> [ %v, %entry ], [ %u, %if ]
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store <3 x i32> %r, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle128:
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; GCN: v_cmp_neq_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.0
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: v_add_i32_e32
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; GCN: s_mov_b64 vcc, [[CMP]]
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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; GCN: buffer_store_dwordx4
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle128(ptr addrspace(1) %out, ptr addrspace(1) %in, float %cnd) #0 {
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entry:
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%v = load <4 x i32>, ptr addrspace(1) %in
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%cc = fcmp oeq float %cnd, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = add <4 x i32> %v, %v
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br label %endif
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endif:
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%r = phi <4 x i32> [ %v, %entry ], [ %u, %if ]
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store <4 x i32> %r, ptr addrspace(1) %out
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ret void
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}
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