9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
61 lines
1.9 KiB
LLVM
61 lines
1.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}else_no_execfix:
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; CHECK: ; %Flow
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; CHECK-NEXT: s_andn2_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]], [[DST]]
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define amdgpu_ps float @else_no_execfix(i32 %z, float %v) #0 {
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main_body:
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%cc = icmp sgt i32 %z, 5
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br i1 %cc, label %if, label %else
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if:
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%v.if = fmul float %v, 2.0
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br label %end
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else:
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%v.else = fmul float %v, 3.0
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br label %end
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end:
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%r = phi float [ %v.if, %if ], [ %v.else, %else ]
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ret float %r
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}
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; CHECK-LABEL: {{^}}else_execfix_leave_wqm:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b64 [[INIT_EXEC:s\[[0-9]+:[0-9]+\]]], exec
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; CHECK: ; %Flow
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; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
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; CHECK-NEXT: s_and_b64 exec, exec, [[INIT_EXEC]]
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; CHECK-NEXT: s_and_b64 [[AND_INIT:s\[[0-9]+:[0-9]+\]]], exec, [[DST]]
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; CHECK-NEXT: s_xor_b64 exec, exec, [[AND_INIT]]
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; CHECK-NEXT: s_cbranch_execz
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define amdgpu_ps void @else_execfix_leave_wqm(i32 %z, float %v) #0 {
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main_body:
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%cc = icmp sgt i32 %z, 5
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br i1 %cc, label %if, label %else
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if:
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%v.if = fmul float %v, 2.0
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br label %end
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else:
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%c = fmul float %v, 3.0
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%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%v.else = extractelement <4 x float> %tex, i32 0
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br label %end
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end:
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%r = phi float [ %v.if, %if ], [ %v.else, %else ]
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call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %r, ptr addrspace(8) undef, i32 0, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.raw.ptr.buffer.store.f32(float, ptr addrspace(8), i32, i32, i32 immarg) #1
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declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 immarg, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind writeonly }
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attributes #2 = { nounwind readonly }
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