9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
51 lines
1.8 KiB
LLVM
51 lines
1.8 KiB
LLVM
; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=GCN
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; GCN-LABEL: and_zext:
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; GCN: v_and_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
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define amdgpu_kernel void @and_zext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%id = call i32 @llvm.amdgcn.workitem.id.x() #1
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%ptr = getelementptr i16, ptr addrspace(1) %in, i32 %id
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%a = load i16, ptr addrspace(1) %in
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%b = load i16, ptr addrspace(1) %ptr
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%c = add i16 %a, %b
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%val16 = and i16 %c, %a
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%val32 = zext i16 %val16 to i32
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store i32 %val32, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: or_zext:
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; GCN: v_or_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
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define amdgpu_kernel void @or_zext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%id = call i32 @llvm.amdgcn.workitem.id.x() #1
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%ptr = getelementptr i16, ptr addrspace(1) %in, i32 %id
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%a = load i16, ptr addrspace(1) %in
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%b = load i16, ptr addrspace(1) %ptr
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%c = add i16 %a, %b
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%val16 = or i16 %c, %a
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%val32 = zext i16 %val16 to i32
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store i32 %val32, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: xor_zext:
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; GCN: v_xor_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
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define amdgpu_kernel void @xor_zext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%id = call i32 @llvm.amdgcn.workitem.id.x() #1
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%ptr = getelementptr i16, ptr addrspace(1) %in, i32 %id
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%a = load i16, ptr addrspace(1) %in
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%b = load i16, ptr addrspace(1) %ptr
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%c = add i16 %a, %b
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%val16 = xor i16 %c, %a
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%val32 = zext i16 %val16 to i32
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store i32 %val32, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #1 = { nounwind readnone }
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