9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
133 lines
4.8 KiB
LLVM
133 lines
4.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare float @llvm.ceil.f32(float) nounwind readnone
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declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone
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declare <3 x float> @llvm.ceil.v3f32(<3 x float>) nounwind readnone
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declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone
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declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone
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declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone
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; FUNC-LABEL: {{^}}fceil_f32:
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; SI: v_ceil_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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define amdgpu_kernel void @fceil_f32(ptr addrspace(1) %out, float %x) {
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%y = call float @llvm.ceil.f32(float %x) nounwind readnone
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store float %y, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v2f32:
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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define amdgpu_kernel void @fceil_v2f32(ptr addrspace(1) %out, <2 x float> %x) {
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%y = call <2 x float> @llvm.ceil.v2f32(<2 x float> %x) nounwind readnone
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store <2 x float> %y, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v3f32:
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; FIXME-SI: v_ceil_f32_e32
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; FIXME-SI: v_ceil_f32_e32
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; FIXME-SI: v_ceil_f32_e32
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; FIXME-EG: v3 is treated as v2 and v1, hence 2 stores
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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define amdgpu_kernel void @fceil_v3f32(ptr addrspace(1) %out, <3 x float> %x) {
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%y = call <3 x float> @llvm.ceil.v3f32(<3 x float> %x) nounwind readnone
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store <3 x float> %y, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v4f32:
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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; EG: CEIL {{\*? *}}[[RESULT]]
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define amdgpu_kernel void @fceil_v4f32(ptr addrspace(1) %out, <4 x float> %x) {
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%y = call <4 x float> @llvm.ceil.v4f32(<4 x float> %x) nounwind readnone
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store <4 x float> %y, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v8f32:
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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define amdgpu_kernel void @fceil_v8f32(ptr addrspace(1) %out, <8 x float> %x) {
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%y = call <8 x float> @llvm.ceil.v8f32(<8 x float> %x) nounwind readnone
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store <8 x float> %y, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v16f32:
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; SI: v_ceil_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT3:T[0-9]+]]{{\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT4:T[0-9]+]]{{\.[XYZW]}}
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT1]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT2]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT3]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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; EG-DAG: CEIL {{\*? *}}[[RESULT4]]
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define amdgpu_kernel void @fceil_v16f32(ptr addrspace(1) %out, <16 x float> %x) {
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%y = call <16 x float> @llvm.ceil.v16f32(<16 x float> %x) nounwind readnone
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store <16 x float> %y, ptr addrspace(1) %out
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ret void
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}
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