9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
197 lines
8.8 KiB
LLVM
197 lines
8.8 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=verde -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=verde -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI %s
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; GCN-LABEL: {{^}}fmuladd_f64:
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; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fmuladd_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r2 = load double, ptr addrspace(1) %in3
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%r3 = tail call double @llvm.fmuladd.f64(double %r0, double %r1, double %r2)
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store double %r3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}fmul_fadd_f64:
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; GCN-CONTRACT: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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; GCN-STRICT: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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; GCN-STRICT: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fmul_fadd_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r2 = load double, ptr addrspace(1) %in3
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%tmp = fmul double %r0, %r1
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%r3 = fadd double %tmp, %r2
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store double %r3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}fmul_fadd_contract_f64:
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; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fmul_fadd_contract_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2, ptr addrspace(1) %in3) #0 {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r2 = load double, ptr addrspace(1) %in3
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%tmp = fmul contract double %r0, %r1
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%r3 = fadd contract double %tmp, %r2
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store double %r3, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_a_a_b_f64:
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; GCN: {{buffer|flat}}_load_dwordx2 [[R1:v\[[0-9]+:[0-9]+\]]],
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; GCN: {{buffer|flat}}_load_dwordx2 [[R2:v\[[0-9]+:[0-9]+\]]],
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; GCN-STRICT: v_add_f64 [[TMP:v\[[0-9]+:[0-9]+\]]], [[R1]], [[R1]]
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; GCN-STRICT: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[TMP]], [[R2]]
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; GCN-CONTRACT: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[R1]], 2.0, [[R2]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fadd_a_a_b_f64(ptr addrspace(1) %out,
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ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1
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%gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%r0 = load volatile double, ptr addrspace(1) %gep.0
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%r1 = load volatile double, ptr addrspace(1) %gep.1
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%add.0 = fadd double %r0, %r0
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%add.1 = fadd double %add.0, %r1
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store double %add.1, ptr addrspace(1) %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_b_a_a_f64:
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; GCN: {{buffer|flat}}_load_dwordx2 [[R1:v\[[0-9]+:[0-9]+\]]],
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; GCN: {{buffer|flat}}_load_dwordx2 [[R2:v\[[0-9]+:[0-9]+\]]],
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; GCN-STRICT: v_add_f64 [[TMP:v\[[0-9]+:[0-9]+\]]], [[R1]], [[R1]]
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; GCN-STRICT: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[R2]], [[TMP]]
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; GCN-CONTRACT: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[R1]], 2.0, [[R2]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fadd_b_a_a_f64(ptr addrspace(1) %out,
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ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1
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%gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%r0 = load volatile double, ptr addrspace(1) %gep.0
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%r1 = load volatile double, ptr addrspace(1) %gep.1
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%add.0 = fadd double %r0, %r0
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%add.1 = fadd double %r1, %add.0
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store double %add.1, ptr addrspace(1) %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}mad_sub_f64:
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; GCN-STRICT: v_mul_f64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}
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; GCN-STRICT: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+:[0-9]+\]}}
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; GCN-CONTRACT: v_fma_f64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @mad_sub_f64(ptr addrspace(1) noalias nocapture %out, ptr addrspace(1) noalias nocapture readonly %ptr) #1 {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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%tid.ext = sext i32 %tid to i64
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%gep0 = getelementptr double, ptr addrspace(1) %ptr, i64 %tid.ext
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%add1 = add i64 %tid.ext, 1
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%gep1 = getelementptr double, ptr addrspace(1) %ptr, i64 %add1
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%add2 = add i64 %tid.ext, 2
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%gep2 = getelementptr double, ptr addrspace(1) %ptr, i64 %add2
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%outgep = getelementptr double, ptr addrspace(1) %out, i64 %tid.ext
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%a = load volatile double, ptr addrspace(1) %gep0, align 8
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%b = load volatile double, ptr addrspace(1) %gep1, align 8
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%c = load volatile double, ptr addrspace(1) %gep2, align 8
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%mul = fmul double %a, %b
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%sub = fsub double %mul, %c
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store double %sub, ptr addrspace(1) %outgep, align 8
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ret void
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}
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; GCN-LABEL: {{^}}fadd_a_a_b_f64_fast_add0:
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; GCN-STRICT: v_add_f64
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; GCN-STRICT: v_add_f64
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; GCN-CONTRACT: v_fma_f64
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define amdgpu_kernel void @fadd_a_a_b_f64_fast_add0(ptr addrspace(1) %out,
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ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1
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%gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%r0 = load volatile double, ptr addrspace(1) %gep.0
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%r1 = load volatile double, ptr addrspace(1) %gep.1
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%add.0 = fadd fast double %r0, %r0
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%add.1 = fadd double %add.0, %r1
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store double %add.1, ptr addrspace(1) %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_a_a_b_f64_fast_add1:
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; GCN-STRICT: v_add_f64
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; GCN-STRICT: v_add_f64
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; GCN-CONTRACT: v_fma_f64
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define amdgpu_kernel void @fadd_a_a_b_f64_fast_add1(ptr addrspace(1) %out,
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ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1
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%gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%r0 = load volatile double, ptr addrspace(1) %gep.0
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%r1 = load volatile double, ptr addrspace(1) %gep.1
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%add.0 = fadd double %r0, %r0
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%add.1 = fadd fast double %add.0, %r1
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store double %add.1, ptr addrspace(1) %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_a_a_b_f64_fast:
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; GCN: v_fma_f64
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define amdgpu_kernel void @fadd_a_a_b_f64_fast(ptr addrspace(1) %out,
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ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%gep.1 = getelementptr double, ptr addrspace(1) %gep.0, i32 1
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%gep.out = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%r0 = load volatile double, ptr addrspace(1) %gep.0
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%r1 = load volatile double, ptr addrspace(1) %gep.1
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%add.0 = fadd fast double %r0, %r0
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%add.1 = fadd fast double %add.0, %r1
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store double %add.1, ptr addrspace(1) %gep.out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare double @llvm.fmuladd.f64(double, double, double) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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