9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
29 lines
1.1 KiB
LLVM
29 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX10
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declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float)
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declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg)
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; Check that this constant is not folded into the v_fmaak_f32 instruction.
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; GFX10-LABEL: _amdgpu_ps_main:
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; GFX10: v_mov_b32_e32 v1, 0x40490fdb
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; GFX10: v_fmaak_f32 v1, v0, v1, 0xbfc90fdb
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define amdgpu_ps void @_amdgpu_ps_main(float %arg) {
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bb:
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%i = fmul reassoc nnan nsz arcp contract afn float %arg, 0x400921FB60000000
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%i1 = fadd reassoc nnan nsz arcp contract afn float %i, 0xBFF921FB60000000
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%i2 = fmul reassoc nnan nsz arcp contract afn float %i1, %arg
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br label %bb3
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bb3:
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br label %bb4
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bb4:
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%i5 = fadd reassoc nnan nsz arcp contract afn float 0x400921FB60000000, %i2
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br label %bb6
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bb6:
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%i7 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %i5, float 0.000000e+00)
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> zeroinitializer, <2 x half> %i7, i1 false, i1 false)
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ret void
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}
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