9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
142 lines
5.2 KiB
LLVM
142 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,FORCESC0SC1 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx941 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,FORCESC0SC1 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs -mattr=-forcestoresc1 < %s | FileCheck --check-prefixes=GCN,NOSC0SC1 %s
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define amdgpu_kernel void @store_global(ptr addrspace(1) %ptr) {
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; FORCESC0SC1-LABEL: store_global:
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; FORCESC0SC1: ; %bb.0: ; %entry
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; FORCESC0SC1-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; FORCESC0SC1-NEXT: v_mov_b32_e32 v0, 0
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; FORCESC0SC1-NEXT: v_mov_b32_e32 v1, 1.0
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; FORCESC0SC1-NEXT: s_waitcnt lgkmcnt(0)
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; FORCESC0SC1-NEXT: global_store_dword v0, v1, s[0:1] sc0 sc1
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; FORCESC0SC1-NEXT: s_endpgm
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;
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; NOSC0SC1-LABEL: store_global:
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; NOSC0SC1: ; %bb.0: ; %entry
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; NOSC0SC1-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; NOSC0SC1-NEXT: v_mov_b32_e32 v0, 0
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; NOSC0SC1-NEXT: v_mov_b32_e32 v1, 1.0
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; NOSC0SC1-NEXT: s_waitcnt lgkmcnt(0)
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; NOSC0SC1-NEXT: global_store_dword v0, v1, s[0:1]
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; NOSC0SC1-NEXT: s_endpgm
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entry:
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store float 1.000000e+00, ptr addrspace(1) %ptr, align 4
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ret void
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}
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define amdgpu_kernel void @store_flat(ptr addrspace(0) %ptr) {
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; FORCESC0SC1-LABEL: store_flat:
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; FORCESC0SC1: ; %bb.0: ; %entry
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; FORCESC0SC1-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; FORCESC0SC1-NEXT: v_mov_b32_e32 v2, 1.0
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; FORCESC0SC1-NEXT: s_waitcnt lgkmcnt(0)
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; FORCESC0SC1-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
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; FORCESC0SC1-NEXT: flat_store_dword v[0:1], v2 sc0 sc1
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; FORCESC0SC1-NEXT: s_endpgm
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;
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; NOSC0SC1-LABEL: store_flat:
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; NOSC0SC1: ; %bb.0: ; %entry
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; NOSC0SC1-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; NOSC0SC1-NEXT: v_mov_b32_e32 v2, 1.0
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; NOSC0SC1-NEXT: s_waitcnt lgkmcnt(0)
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; NOSC0SC1-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
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; NOSC0SC1-NEXT: flat_store_dword v[0:1], v2
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; NOSC0SC1-NEXT: s_endpgm
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entry:
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store float 1.000000e+00, ptr addrspace(0) %ptr, align 4
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ret void
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}
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define amdgpu_kernel void @store_lds(ptr addrspace(3) %ptr) {
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; GCN-LABEL: store_lds:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s0, s[0:1], 0x24
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; GCN-NEXT: v_mov_b32_e32 v0, 1.0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v1, s0
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; GCN-NEXT: ds_write_b32 v1, v0
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; GCN-NEXT: s_endpgm
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entry:
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store float 1.000000e+00, ptr addrspace(3) %ptr, align 4
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ret void
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}
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define amdgpu_kernel void @store_scratch(ptr addrspace(5) %ptr) {
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; FORCESC0SC1-LABEL: store_scratch:
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; FORCESC0SC1: ; %bb.0: ; %entry
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; FORCESC0SC1-NEXT: s_load_dword s0, s[0:1], 0x24
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; FORCESC0SC1-NEXT: v_mov_b32_e32 v0, 1.0
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; FORCESC0SC1-NEXT: s_waitcnt lgkmcnt(0)
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; FORCESC0SC1-NEXT: scratch_store_dword off, v0, s0 sc0 sc1
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; FORCESC0SC1-NEXT: s_endpgm
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;
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; NOSC0SC1-LABEL: store_scratch:
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; NOSC0SC1: ; %bb.0: ; %entry
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; NOSC0SC1-NEXT: s_load_dword s0, s[0:1], 0x24
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; NOSC0SC1-NEXT: v_mov_b32_e32 v0, 1.0
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; NOSC0SC1-NEXT: s_waitcnt lgkmcnt(0)
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; NOSC0SC1-NEXT: scratch_store_dword off, v0, s0
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; NOSC0SC1-NEXT: s_endpgm
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entry:
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store float 1.000000e+00, ptr addrspace(5) %ptr, align 4
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ret void
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}
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define amdgpu_ps void @store_buffer(<4 x i32> inreg %rsrc, float %data, i32 %index) {
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; FORCESC0SC1-LABEL: store_buffer:
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; FORCESC0SC1: ; %bb.0: ; %main_body
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; FORCESC0SC1-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen sc0 sc1
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; FORCESC0SC1-NEXT: s_endpgm
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;
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; NOSC0SC1-LABEL: store_buffer:
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; NOSC0SC1: ; %bb.0: ; %main_body
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; NOSC0SC1-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen
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; NOSC0SC1-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
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ret void
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}
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define amdgpu_kernel void @store_global_atomic(ptr addrspace(1) %ptr) {
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; FORCESC0SC1-LABEL: store_global_atomic:
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; FORCESC0SC1: ; %bb.0: ; %entry
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; FORCESC0SC1-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; FORCESC0SC1-NEXT: v_mov_b32_e32 v0, 0
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; FORCESC0SC1-NEXT: v_mov_b32_e32 v1, 1.0
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; FORCESC0SC1-NEXT: buffer_wbl2 sc1
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; FORCESC0SC1-NEXT: s_waitcnt lgkmcnt(0)
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; FORCESC0SC1-NEXT: global_store_dword v0, v1, s[0:1] sc0 sc1
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; FORCESC0SC1-NEXT: s_endpgm
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;
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; NOSC0SC1-LABEL: store_global_atomic:
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; NOSC0SC1: ; %bb.0: ; %entry
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; NOSC0SC1-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; NOSC0SC1-NEXT: v_mov_b32_e32 v0, 0
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; NOSC0SC1-NEXT: v_mov_b32_e32 v1, 1.0
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; NOSC0SC1-NEXT: buffer_wbl2 sc1
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; NOSC0SC1-NEXT: s_waitcnt lgkmcnt(0)
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; NOSC0SC1-NEXT: global_store_dword v0, v1, s[0:1] sc1
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; NOSC0SC1-NEXT: s_endpgm
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entry:
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store atomic float 1.000000e+00, ptr addrspace(1) %ptr syncscope("agent-one-as") seq_cst, align 4
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ret void
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}
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define amdgpu_kernel void @store_global_atomic_system(ptr addrspace(1) %ptr) {
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; GCN-LABEL: store_global_atomic_system:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: v_mov_b32_e32 v1, 1.0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_store_dword v0, v1, s[0:1] sc0 sc1
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; GCN-NEXT: s_endpgm
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store atomic float 1.000000e+00, ptr addrspace(1) %ptr monotonic, align 4
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ret void
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}
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declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1)
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