9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
73 lines
3.0 KiB
LLVM
73 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6 %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
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declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
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define amdgpu_kernel void @test_convert_fp16_to_fp64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
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; GFX6-LABEL: test_convert_fp16_to_fp64:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s10, s6
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; GFX6-NEXT: s_mov_b32 s11, s7
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_mov_b32 s8, s2
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; GFX6-NEXT: s_mov_b32 s9, s3
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; GFX6-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; GFX6-NEXT: s_mov_b32 s4, s0
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; GFX6-NEXT: s_mov_b32 s5, s1
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX6-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
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; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX8-LABEL: test_convert_fp16_to_fp64:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX8-NEXT: s_mov_b32 s7, 0xf000
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; GFX8-NEXT: s_mov_b32 s6, -1
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; GFX8-NEXT: s_mov_b32 s10, s6
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; GFX8-NEXT: s_mov_b32 s11, s7
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_mov_b32 s8, s2
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; GFX8-NEXT: s_mov_b32 s9, s3
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; GFX8-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; GFX8-NEXT: s_mov_b32 s4, s0
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; GFX8-NEXT: s_mov_b32 s5, s1
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; GFX8-NEXT: s_waitcnt vmcnt(0)
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; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX8-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
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; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GFX8-NEXT: s_endpgm
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;
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; GFX11-LABEL: test_convert_fp16_to_fp64:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX11-NEXT: s_mov_b32 s6, -1
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; GFX11-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-NEXT: s_mov_b32 s10, s6
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; GFX11-NEXT: s_mov_b32 s11, s7
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_mov_b32 s8, s2
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; GFX11-NEXT: s_mov_b32 s9, s3
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; GFX11-NEXT: s_mov_b32 s4, s0
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; GFX11-NEXT: buffer_load_u16 v0, off, s[8:11], 0
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; GFX11-NEXT: s_mov_b32 s5, s1
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
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; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[4:7], 0
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%val = load i16, ptr addrspace(1) %in, align 2
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%cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone
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store double %cvt, ptr addrspace(1) %out, align 4
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ret void
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}
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