9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
72 lines
3.0 KiB
LLVM
72 lines
3.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=CHECK %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
|
|
|
|
define amdgpu_kernel void @use_gep_address_space(ptr addrspace(3) %array) nounwind {
|
|
; CHECK-LABEL: {{^}}use_gep_address_space:
|
|
; CHECK: v_mov_b32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}}
|
|
; CHECK: ds_write_b32 [[PTR]], v{{[0-9]+}} offset:64
|
|
%p = getelementptr [1024 x i32], ptr addrspace(3) %array, i16 0, i16 16
|
|
store i32 99, ptr addrspace(3) %p
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: {{^}}use_gep_address_space_large_offset:
|
|
; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
|
|
; SI, which is why it is being OR'd with the base pointer.
|
|
; SI: s_bitset1_b32
|
|
; CI: s_add_i32
|
|
; CHECK: ds_write_b32
|
|
define amdgpu_kernel void @use_gep_address_space_large_offset(ptr addrspace(3) %array) nounwind {
|
|
%p = getelementptr [1024 x i32], ptr addrspace(3) %array, i16 0, i16 16384
|
|
store i32 99, ptr addrspace(3) %p
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: {{^}}gep_as_vector_v4:
|
|
; SI: s_add_i32
|
|
; SI: s_add_i32
|
|
; SI: s_add_i32
|
|
; SI: s_add_i32
|
|
|
|
; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
|
|
; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
|
|
; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
|
|
; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
|
|
|
|
; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
|
|
; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
|
|
; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
|
|
; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
|
|
; CHECK: s_endpgm
|
|
define amdgpu_kernel void @gep_as_vector_v4(<4 x ptr addrspace(3)> %array) nounwind {
|
|
%p = getelementptr [1024 x i32], <4 x ptr addrspace(3)> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
|
|
%p0 = extractelement <4 x ptr addrspace(3)> %p, i32 0
|
|
%p1 = extractelement <4 x ptr addrspace(3)> %p, i32 1
|
|
%p2 = extractelement <4 x ptr addrspace(3)> %p, i32 2
|
|
%p3 = extractelement <4 x ptr addrspace(3)> %p, i32 3
|
|
store i32 99, ptr addrspace(3) %p0
|
|
store i32 99, ptr addrspace(3) %p1
|
|
store i32 99, ptr addrspace(3) %p2
|
|
store i32 99, ptr addrspace(3) %p3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: {{^}}gep_as_vector_v2:
|
|
; SI: s_add_i32
|
|
; SI: s_add_i32
|
|
; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
|
|
; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
|
|
; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
|
|
; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
|
|
; CHECK: s_endpgm
|
|
define amdgpu_kernel void @gep_as_vector_v2(<2 x ptr addrspace(3)> %array) nounwind {
|
|
%p = getelementptr [1024 x i32], <2 x ptr addrspace(3)> %array, <2 x i16> zeroinitializer, <2 x i16> <i16 16, i16 16>
|
|
%p0 = extractelement <2 x ptr addrspace(3)> %p, i32 0
|
|
%p1 = extractelement <2 x ptr addrspace(3)> %p, i32 1
|
|
store i32 99, ptr addrspace(3) %p0
|
|
store i32 99, ptr addrspace(3) %p1
|
|
ret void
|
|
}
|
|
|