9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
47 lines
1.7 KiB
LLVM
47 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs -disable-block-placement < %s | FileCheck %s
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; Check that invariant compare is hoisted out of the loop.
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; At the same time condition shall not be serialized into a VGPR and deserialized later
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; using another v_cmp + v_cndmask, but used directly in s_and_saveexec_b64.
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; CHECK: v_cmp_{{..}}_u32_e{{32|64}} [[COND:s\[[0-9]+:[0-9]+\]|vcc]]
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; CHECK: BB0_1:
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; CHECK-NOT: v_cmp
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; CHECK-NOT: v_cndmask
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; CHECK: s_and_saveexec_b64 s[{{[0-9]+:[0-9]+}}], [[COND]]
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; CHECK: ; %bb.2:
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define amdgpu_kernel void @hoist_cond(ptr addrspace(1) nocapture %arg, ptr addrspace(1) noalias nocapture readonly %arg1, i32 %arg3, i32 %arg4) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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%tmp5 = icmp ult i32 %tmp, %arg3
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br label %bb1
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bb1: ; preds = %bb3, %bb
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%tmp7 = phi i32 [ %arg4, %bb ], [ %tmp16, %bb3 ]
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%tmp8 = phi float [ 0.000000e+00, %bb ], [ %tmp15, %bb3 ]
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br i1 %tmp5, label %bb2, label %bb3
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bb2: ; preds = %bb1
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%tmp10 = zext i32 %tmp7 to i64
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%tmp11 = getelementptr inbounds float, ptr addrspace(1) %arg1, i64 %tmp10
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%tmp12 = load float, ptr addrspace(1) %tmp11, align 4
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br label %bb3
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bb3: ; preds = %bb2, %bb1
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%tmp14 = phi float [ %tmp12, %bb2 ], [ 0.000000e+00, %bb1 ]
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%tmp15 = fadd float %tmp8, %tmp14
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%tmp16 = add i32 %tmp7, -1
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%tmp17 = icmp eq i32 %tmp16, 0
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br i1 %tmp17, label %bb4, label %bb1
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bb4: ; preds = %bb3
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store float %tmp15, ptr addrspace(1) %arg, align 4
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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