9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
125 lines
4.9 KiB
LLVM
125 lines
4.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-ALLOCA16,SI %s
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; RUN: llc -mtriple=amdgcn -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-ALLOCA4,SI %s
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; RUN: llc -mtriple=amdgcn -mattr=+promote-alloca -disable-promote-alloca-to-vector -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-PROMOTE,SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+promote-alloca -disable-promote-alloca-to-vector -verify-machineinstrs < %s | FileCheck --check-prefixes=CI-PROMOTE,SI %s
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declare void @llvm.amdgcn.s.barrier() #0
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; SI-LABEL: {{^}}private_access_f64_alloca:
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; SI-ALLOCA16: buffer_store_dwordx2
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; SI-ALLOCA16: buffer_load_dwordx2
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_read_b64
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; CI-PROMOTE: ds_write_b64
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; CI-PROMOTE: ds_read_b64
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define amdgpu_kernel void @private_access_f64_alloca(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i32 %b) #1 {
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%val = load double, ptr addrspace(1) %in, align 8
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%array = alloca [8 x double], align 8, addrspace(5)
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%ptr = getelementptr inbounds [8 x double], ptr addrspace(5) %array, i32 0, i32 %b
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store double %val, ptr addrspace(5) %ptr, align 8
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call void @llvm.amdgcn.s.barrier()
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%result = load double, ptr addrspace(5) %ptr, align 8
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store double %result, ptr addrspace(1) %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}private_access_v2f64_alloca:
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; SI-ALLOCA16: buffer_store_dwordx4
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; SI-ALLOCA16: buffer_load_dwordx4
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_read_b64
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; SI-PROMOTE: ds_read_b64
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; CI-PROMOTE: ds_write_b128
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; CI-PROMOTE: ds_read_b128
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define amdgpu_kernel void @private_access_v2f64_alloca(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i32 %b) #1 {
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%val = load <2 x double>, ptr addrspace(1) %in, align 16
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%array = alloca [4 x <2 x double>], align 16, addrspace(5)
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%ptr = getelementptr inbounds [4 x <2 x double>], ptr addrspace(5) %array, i32 0, i32 %b
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store <2 x double> %val, ptr addrspace(5) %ptr, align 16
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call void @llvm.amdgcn.s.barrier()
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%result = load <2 x double>, ptr addrspace(5) %ptr, align 16
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store <2 x double> %result, ptr addrspace(1) %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}private_access_i64_alloca:
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; SI-ALLOCA16: buffer_store_dwordx2
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; SI-ALLOCA16: buffer_load_dwordx2
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_read_b64
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; CI-PROMOTE: ds_write_b64
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; CI-PROMOTE: ds_read_b64
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define amdgpu_kernel void @private_access_i64_alloca(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i32 %b) #1 {
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%val = load i64, ptr addrspace(1) %in, align 8
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%array = alloca [8 x i64], align 8, addrspace(5)
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%ptr = getelementptr inbounds [8 x i64], ptr addrspace(5) %array, i32 0, i32 %b
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store i64 %val, ptr addrspace(5) %ptr, align 8
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call void @llvm.amdgcn.s.barrier()
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%result = load i64, ptr addrspace(5) %ptr, align 8
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store i64 %result, ptr addrspace(1) %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}private_access_v2i64_alloca:
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; SI-ALLOCA16: buffer_store_dwordx4
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; SI-ALLOCA16: buffer_load_dwordx4
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_store_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-ALLOCA4: buffer_load_dword v
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_write_b64
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; SI-PROMOTE: ds_read_b64
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; SI-PROMOTE: ds_read_b64
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; CI-PROMOTE: ds_write_b128
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; CI-PROMOTE: ds_read_b128
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define amdgpu_kernel void @private_access_v2i64_alloca(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i32 %b) #1 {
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%val = load <2 x i64>, ptr addrspace(1) %in, align 16
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%array = alloca [4 x <2 x i64>], align 16, addrspace(5)
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%ptr = getelementptr inbounds [4 x <2 x i64>], ptr addrspace(5) %array, i32 0, i32 %b
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store <2 x i64> %val, ptr addrspace(5) %ptr, align 16
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call void @llvm.amdgcn.s.barrier()
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%result = load <2 x i64>, ptr addrspace(5) %ptr, align 16
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store <2 x i64> %result, ptr addrspace(1) %out, align 16
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ret void
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}
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attributes #0 = { convergent nounwind }
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attributes #1 = { nounwind "amdgpu-waves-per-eu"="1,2" "amdgpu-flat-work-group-size"="64,128" }
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