9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
58 lines
2.1 KiB
LLVM
58 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}inline_asm_input_v2i16:
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; GCN: s_mov_b32 s{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @inline_asm_input_v2i16(ptr addrspace(1) %out, <2 x i16> %in) #0 {
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entry:
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%val = call i32 asm "s_mov_b32 $0, $1", "=r,r"(<2 x i16> %in) #0
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}inline_asm_input_v2f16:
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; GCN: s_mov_b32 s0, s{{[0-9]+}}
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define amdgpu_kernel void @inline_asm_input_v2f16(ptr addrspace(1) %out, <2 x half> %in) #0 {
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entry:
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%val = call i32 asm "s_mov_b32 $0, $1", "=r,r"(<2 x half> %in) #0
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store i32 %val, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}inline_asm_output_v2i16:
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; GCN: s_mov_b32 s{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @inline_asm_output_v2i16(ptr addrspace(1) %out, i32 %in) #0 {
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entry:
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%val = call <2 x i16> asm "s_mov_b32 $0, $1", "=r,r"(i32 %in) #0
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store <2 x i16> %val, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}inline_asm_output_v2f16:
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; GCN: v_mov_b32 v{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @inline_asm_output_v2f16(ptr addrspace(1) %out, i32 %in) #0 {
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entry:
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%val = call <2 x half> asm "v_mov_b32 $0, $1", "=v,r"(i32 %in) #0
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store <2 x half> %val, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}inline_asm_packed_v2i16:
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; GCN: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @inline_asm_packed_v2i16(ptr addrspace(1) %out, <2 x i16> %in0, <2 x i16> %in1) #0 {
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entry:
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%val = call <2 x i16> asm "v_pk_add_u16 $0, $1, $2", "=v,r,v"(<2 x i16> %in0, <2 x i16> %in1) #0
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store <2 x i16> %val, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}inline_asm_packed_v2f16:
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; GCN: v_pk_add_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @inline_asm_packed_v2f16(ptr addrspace(1) %out, <2 x half> %in0, <2 x half> %in1) #0 {
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entry:
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%val = call <2 x half> asm "v_pk_add_f16 $0, $1, $2", "=v,r,v"(<2 x half> %in0, <2 x half> %in1) #0
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store <2 x half> %val, ptr addrspace(1) %out
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ret void
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}
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attributes #0 = { nounwind }
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