9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
66 lines
1.9 KiB
YAML
66 lines
1.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-pre-emit-peephole -amdgpu-skip-threshold=1 -verify-machineinstrs %s -o - | FileCheck %s
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# Make sure mandatory skips are inserted to ensure GWS ops aren't run with exec = 0
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---
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name: skip_gws_init
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body: |
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; CHECK-LABEL: name: skip_gws_init
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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bb.2:
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S_ENDPGM 0
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...
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---
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name: skip_gws_barrier
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body: |
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; CHECK-LABEL: name: skip_gws_barrier
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: DS_GWS_BARRIER $vgpr0, 0, implicit $m0, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.1:
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successors: %bb.2
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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DS_GWS_BARRIER $vgpr0, 0, implicit $m0, implicit $exec
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bb.2:
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S_ENDPGM 0
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...
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