9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
58 lines
2.2 KiB
LLVM
58 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
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; RUN: llc -mtriple=amdgcn -mcpu=carrizo -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=ALL %s
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; ALL-LABEL: {{^}}large_alloca_pixel_shader:
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; GCN-DAG: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
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; GCN-DAG: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
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; GCN-DAG: s_mov_b32 s6, -1
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; CI-DAG: s_mov_b32 s7, 0xe8f000
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; VI-DAG: s_mov_b32 s7, 0xe80000
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; GFX9-DAG: s_mov_b32 s7, 0xe00000
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; GCN: s_add_u32 s4, s4, s0
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; GCN: s_addc_u32 s5, s5, 0
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; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[4:7], 0 offen
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; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[4:7], 0 offen
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; ALL: ; ScratchSize: 32772
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define amdgpu_ps void @large_alloca_pixel_shader(i32 %x, i32 %y) #0 {
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%large = alloca [8192 x i32], align 4, addrspace(5)
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%gep = getelementptr [8192 x i32], ptr addrspace(5) %large, i32 0, i32 8191
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store volatile i32 %x, ptr addrspace(5) %gep
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%gep1 = getelementptr [8192 x i32], ptr addrspace(5) %large, i32 0, i32 %y
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%val = load volatile i32, ptr addrspace(5) %gep1
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store volatile i32 %val, ptr addrspace(1) undef
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ret void
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}
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; ALL-LABEL: {{^}}large_alloca_pixel_shader_inreg:
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; GCN-DAG: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
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; GCN-DAG: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
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; GCN-DAG: s_mov_b32 s6, -1
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; CI-DAG: s_mov_b32 s7, 0xe8f000
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; VI-DAG: s_mov_b32 s7, 0xe80000
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; GFX9-DAG: s_mov_b32 s7, 0xe00000
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; GCN: s_add_u32 s4, s4, s2
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; GCN: s_addc_u32 s5, s5, 0
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; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[4:7], 0 offen
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; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[4:7], 0 offen
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; ALL: ; ScratchSize: 32772
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define amdgpu_ps void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #0 {
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%large = alloca [8192 x i32], align 4, addrspace(5)
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%gep = getelementptr [8192 x i32], ptr addrspace(5) %large, i32 0, i32 8191
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store volatile i32 %x, ptr addrspace(5) %gep
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%gep1 = getelementptr [8192 x i32], ptr addrspace(5) %large, i32 0, i32 %y
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%val = load volatile i32, ptr addrspace(5) %gep1
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store volatile i32 %val, ptr addrspace(1) undef
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ret void
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}
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attributes #0 = { nounwind }
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