9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
130 lines
4.0 KiB
LLVM
130 lines
4.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOSI %s
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@compute_lds = external addrspace(3) global [512 x i32], align 16
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; GCN-LABEL: {{^}}store_aligned:
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; GCN: ds_write_b64
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define amdgpu_cs void @store_aligned(ptr addrspace(3) %ptr) #0 {
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entry:
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%ptr.gep.1 = getelementptr i32, ptr addrspace(3) %ptr, i32 1
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store i32 42, ptr addrspace(3) %ptr, align 8
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store i32 43, ptr addrspace(3) %ptr.gep.1
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ret void
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}
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; GCN-LABEL: {{^}}load_aligned:
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; GCN: ds_read_b64
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define amdgpu_cs <2 x float> @load_aligned(ptr addrspace(3) %ptr) #0 {
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entry:
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%ptr.gep.1 = getelementptr i32, ptr addrspace(3) %ptr, i32 1
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%v.0 = load i32, ptr addrspace(3) %ptr, align 8
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%v.1 = load i32, ptr addrspace(3) %ptr.gep.1
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%r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
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%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
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%bc = bitcast <2 x i32> %r.1 to <2 x float>
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ret <2 x float> %bc
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}
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; GCN-LABEL: {{^}}store_global_const_idx:
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; GCN: ds_write2_b32
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define amdgpu_cs void @store_global_const_idx() #0 {
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entry:
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%ptr.a = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 3
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%ptr.b = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 4
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store i32 42, ptr addrspace(3) %ptr.a
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store i32 43, ptr addrspace(3) %ptr.b
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ret void
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}
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; GCN-LABEL: {{^}}load_global_const_idx:
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; GCN: ds_read2_b32
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define amdgpu_cs <2 x float> @load_global_const_idx() #0 {
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entry:
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%ptr.a = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 3
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%ptr.b = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 4
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%v.0 = load i32, ptr addrspace(3) %ptr.a
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%v.1 = load i32, ptr addrspace(3) %ptr.b
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%r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
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%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
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%bc = bitcast <2 x i32> %r.1 to <2 x float>
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ret <2 x float> %bc
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}
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; GCN-LABEL: {{^}}store_global_var_idx_case1:
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; SI: ds_write_b32
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; SI: ds_write_b32
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; NOSI: ds_write2_b32
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define amdgpu_cs void @store_global_var_idx_case1(i32 %idx) #0 {
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entry:
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%ptr.a = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 %idx
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%ptr.b = getelementptr i32, ptr addrspace(3) %ptr.a, i32 1
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store i32 42, ptr addrspace(3) %ptr.a
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store i32 43, ptr addrspace(3) %ptr.b
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ret void
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}
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; GCN-LABEL: {{^}}load_global_var_idx_case1:
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; SI: ds_read_b32
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; SI: ds_read_b32
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; NOSI: ds_read2_b32
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define amdgpu_cs <2 x float> @load_global_var_idx_case1(i32 %idx) #0 {
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entry:
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%ptr.a = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 %idx
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%ptr.b = getelementptr i32, ptr addrspace(3) %ptr.a, i32 1
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%v.0 = load i32, ptr addrspace(3) %ptr.a
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%v.1 = load i32, ptr addrspace(3) %ptr.b
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%r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
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%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
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%bc = bitcast <2 x i32> %r.1 to <2 x float>
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ret <2 x float> %bc
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}
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; GCN-LABEL: {{^}}store_global_var_idx_case2:
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; GCN: ds_write2_b32
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define amdgpu_cs void @store_global_var_idx_case2(i32 %idx) #0 {
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entry:
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%idx.and = and i32 %idx, 255
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%ptr.a = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 %idx.and
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%ptr.b = getelementptr i32, ptr addrspace(3) %ptr.a, i32 1
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store i32 42, ptr addrspace(3) %ptr.a
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store i32 43, ptr addrspace(3) %ptr.b
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ret void
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}
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; GCN-LABEL: {{^}}load_global_var_idx_case2:
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; GCN: ds_read2_b32
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define amdgpu_cs <2 x float> @load_global_var_idx_case2(i32 %idx) #0 {
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entry:
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%idx.and = and i32 %idx, 255
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%ptr.a = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 %idx.and
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%ptr.b = getelementptr i32, ptr addrspace(3) %ptr.a, i32 1
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%v.0 = load i32, ptr addrspace(3) %ptr.a
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%v.1 = load i32, ptr addrspace(3) %ptr.b
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%r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
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%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
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%bc = bitcast <2 x i32> %r.1 to <2 x float>
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ret <2 x float> %bc
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}
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attributes #0 = { nounwind }
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