9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
72 lines
2.2 KiB
YAML
72 lines
2.2 KiB
YAML
# RUN: llc -mtriple=amdgcn -run-pass register-coalescer -o - %s | FileCheck %s
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# Check that coalescer does not create wider register tuple than in source
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# CHECK: - { id: 2, class: vreg_64, preferred-register: '' }
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# CHECK: - { id: 3, class: vreg_64, preferred-register: '' }
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# CHECK: - { id: 4, class: vreg_64, preferred-register: '' }
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# CHECK: - { id: 5, class: vreg_96, preferred-register: '' }
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# CHECK: - { id: 6, class: vreg_96, preferred-register: '' }
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# CHECK: - { id: 7, class: vreg_128, preferred-register: '' }
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# CHECK: - { id: 8, class: vreg_128, preferred-register: '' }
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# No more registers shall be defined
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# CHECK-NEXT: liveins:
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# CHECK: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %4,
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# CHECK: FLAT_STORE_DWORDX3 $vgpr0_vgpr1, %6,
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---
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name: main
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 1, class: sreg_32_xm0, preferred-register: '%1' }
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- { id: 2, class: vreg_64, preferred-register: '%2' }
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- { id: 3, class: vreg_64 }
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- { id: 4, class: vreg_64 }
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- { id: 5, class: vreg_64 }
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- { id: 6, class: vreg_96 }
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- { id: 7, class: vreg_96 }
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- { id: 8, class: vreg_128 }
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- { id: 9, class: vreg_128 }
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liveins:
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- { reg: '$sgpr6', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0.entry:
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liveins: $sgpr0, $vgpr0_vgpr1
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%3 = IMPLICIT_DEF
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undef %4.sub0 = COPY $sgpr0
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%4.sub1 = COPY %3.sub0
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undef %5.sub0 = COPY %4.sub1
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%5.sub1 = COPY %4.sub0
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FLAT_STORE_DWORDX2 $vgpr0_vgpr1, killed %5, 0, 0, implicit $exec, implicit $flat_scr
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%6 = IMPLICIT_DEF
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undef %7.sub0_sub1 = COPY %6
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%7.sub2 = COPY %3.sub0
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FLAT_STORE_DWORDX3 $vgpr0_vgpr1, killed %7, 0, 0, implicit $exec, implicit $flat_scr
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%8 = IMPLICIT_DEF
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undef %9.sub0_sub1_sub2 = COPY %8
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%9.sub3 = COPY %3.sub0
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FLAT_STORE_DWORDX4 $vgpr0_vgpr1, killed %9, 0, 0, implicit $exec, implicit $flat_scr
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...
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