9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
130 lines
4.6 KiB
LLVM
130 lines
4.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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declare half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c)
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; GCN-LABEL: {{^}}div_fixup_f16
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load volatile half, ptr addrspace(1) %a
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%b.val = load volatile half, ptr addrspace(1) %b
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%c.val = load volatile half, ptr addrspace(1) %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half %b.val, half %c.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_a
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; VI: s_movk_i32 s[[A_F16:[0-9]+]], 0x4200{{$}}
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], s[[A_F16]], v[[B_F16]], v[[C_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_a(
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ptr addrspace(1) %r,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%b.val = load volatile half, ptr addrspace(1) %b
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%c.val = load volatile half, ptr addrspace(1) %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half %b.val, half %c.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_b
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; VI: s_movk_i32 s[[B_F16:[0-9]+]], 0x4200{{$}}
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], s[[B_F16]], v[[C_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_b(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load volatile half, ptr addrspace(1) %a
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%c.val = load volatile half, ptr addrspace(1) %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half 3.0, half %c.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_c
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; VI: s_movk_i32 s[[C_F16:[0-9]+]], 0x4200{{$}}
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], s[[C_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_c(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b) {
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entry:
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%a.val = load volatile half, ptr addrspace(1) %a
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%b.val = load volatile half, ptr addrspace(1) %b
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half %b.val, half 3.0)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_a_imm_b
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; VI-DAG: s_movk_i32 [[AB_F16:s[0-9]+]], 0x4200{{$}}
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; GCN-DAG: buffer_load_ushort v[[C_F16:[0-9]+]]
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], [[AB_F16]], [[AB_F16]], v[[C_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_a_imm_b(
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ptr addrspace(1) %r,
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ptr addrspace(1) %c) {
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entry:
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%c.val = load volatile half, ptr addrspace(1) %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half 3.0, half %c.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_b_imm_c
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; VI-DAG: s_movk_i32 [[BC_F16:s[0-9]+]], 0x4200{{$}}
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; GCN-DAG: buffer_load_ushort v[[A_F16:[0-9]+]]
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], [[BC_F16]], [[BC_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_b_imm_c(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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entry:
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%a.val = load half, ptr addrspace(1) %a
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half 3.0, half 3.0)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_a_imm_c
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; VI-DAG: s_movk_i32 [[AC_F16:s[0-9]+]], 0x4200{{$}}
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; GCN-DAG: buffer_load_ushort v[[B_F16:[0-9]+]]
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], [[AC_F16]], v[[B_F16]], [[AC_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_a_imm_c(
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ptr addrspace(1) %r,
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ptr addrspace(1) %b) {
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entry:
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%b.val = load half, ptr addrspace(1) %b
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half %b.val, half 3.0)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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