9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
104 lines
4.2 KiB
LLVM
104 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-SDAG
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-GISEL
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declare void @llvm.amdgcn.exp.row.i32(i32, i32, i32, i32, i32, i32, i1, i32)
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declare void @llvm.amdgcn.exp.row.f32(i32, i32, float, float, float, float, i1, i32)
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declare i32 @llvm.amdgcn.workitem.id.x()
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define amdgpu_kernel void @undef_i32() #0 {
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; GFX11-LABEL: undef_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_mov_b32 m0, 0
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; GFX11-NEXT: exp pos0 off, off, off, off row_en
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; GFX11-NEXT: exp pos1 off, off, off, off done row_en
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; GFX11-NEXT: s_endpgm
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call void @llvm.amdgcn.exp.row.i32(i32 12, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i1 false, i32 0)
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call void @llvm.amdgcn.exp.row.i32(i32 13, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i1 true, i32 0)
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ret void
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}
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define amdgpu_kernel void @undef_f32() #0 {
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; GFX11-LABEL: undef_f32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_mov_b32 m0, 0
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; GFX11-NEXT: exp pos0 off, off, off, off row_en
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; GFX11-NEXT: exp pos1 off, off, off, off done row_en
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; GFX11-NEXT: s_endpgm
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call void @llvm.amdgcn.exp.row.f32(i32 12, i32 0, float undef, float undef, float undef, float undef, i1 false, i32 0)
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call void @llvm.amdgcn.exp.row.f32(i32 13, i32 0, float undef, float undef, float undef, float undef, i1 true, i32 0)
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ret void
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}
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define amdgpu_kernel void @zero_i32() #0 {
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; GFX11-LABEL: zero_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v0, 0
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; GFX11-NEXT: s_mov_b32 m0, 0
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; GFX11-NEXT: exp pos0 v0, v0, v0, off row_en
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; GFX11-NEXT: exp pos1 v0, v0, v0, off done row_en
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; GFX11-NEXT: s_endpgm
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call void @llvm.amdgcn.exp.row.i32(i32 12, i32 7, i32 0, i32 0, i32 0, i32 undef, i1 false, i32 0)
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call void @llvm.amdgcn.exp.row.i32(i32 13, i32 7, i32 0, i32 0, i32 0, i32 undef, i1 true, i32 0)
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ret void
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}
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define amdgpu_kernel void @one_f32() #0 {
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; GFX11-LABEL: one_f32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_mov_b32_e32 v0, 1.0
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; GFX11-NEXT: s_mov_b32 m0, 0
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; GFX11-NEXT: exp pos0 v0, v0, v0, off row_en
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; GFX11-NEXT: exp pos1 v0, v0, v0, off done row_en
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; GFX11-NEXT: s_endpgm
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call void @llvm.amdgcn.exp.row.f32(i32 12, i32 7, float 1.0, float 1.0, float 1.0, float undef, i1 false, i32 0)
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call void @llvm.amdgcn.exp.row.f32(i32 13, i32 7, float 1.0, float 1.0, float 1.0, float undef, i1 true, i32 0)
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ret void
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}
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define amdgpu_kernel void @id_i32() #0 {
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; GFX11-LABEL: id_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_mov_b32 m0, 0
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; GFX11-NEXT: exp pos0 v0, off, off, off done row_en
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; GFX11-NEXT: s_endpgm
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 undef, i32 undef, i32 undef, i1 true, i32 0)
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ret void
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}
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define amdgpu_kernel void @id_arg_i32(i32 %row) #0 {
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; GFX11-LABEL: id_arg_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x24
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_mov_b32 m0, s0
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; GFX11-NEXT: exp pos0 v0, off, off, off done row_en
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; GFX11-NEXT: s_endpgm
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 undef, i32 undef, i32 undef, i1 true, i32 %row)
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ret void
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}
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; Divergent row number just causes a readfirstlane for now.
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define amdgpu_kernel void @id_row_i32() #0 {
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; GFX11-SDAG-LABEL: id_row_i32:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v0
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; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0x63
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; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX11-SDAG-NEXT: s_mov_b32 m0, s0
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; GFX11-SDAG-NEXT: exp pos0 v0, off, off, off done row_en
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; GFX11-SDAG-NEXT: s_endpgm
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;
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; GFX11-GISEL-LABEL: id_row_i32:
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; GFX11-GISEL: ; %bb.0:
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; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0x63
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; GFX11-GISEL-NEXT: v_readfirstlane_b32 m0, v0
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; GFX11-GISEL-NEXT: exp pos0 v1, off, off, off done row_en
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; GFX11-GISEL-NEXT: s_endpgm
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 99, i32 undef, i32 undef, i32 undef, i1 true, i32 %id)
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ret void
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}
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