9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
75 lines
3.1 KiB
LLVM
75 lines
3.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare float @llvm.fabs.f32(float) #0
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declare float @llvm.copysign.f32(float, float) #0
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declare double @llvm.fabs.f64(double) #0
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declare i32 @llvm.amdgcn.frexp.exp.i32.f32(float) #0
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declare i32 @llvm.amdgcn.frexp.exp.i32.f64(double) #0
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; GCN-LABEL: {{^}}s_test_frexp_exp_f32:
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; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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define amdgpu_kernel void @s_test_frexp_exp_f32(ptr addrspace(1) %out, float %src) #1 {
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_fabs_frexp_exp_f32:
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; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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define amdgpu_kernel void @s_test_fabs_frexp_exp_f32(ptr addrspace(1) %out, float %src) #1 {
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%fabs.src = call float @llvm.fabs.f32(float %src)
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %fabs.src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_exp_f32:
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; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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define amdgpu_kernel void @s_test_fneg_fabs_frexp_exp_f32(ptr addrspace(1) %out, float %src) #1 {
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%fabs.src = call float @llvm.fabs.f32(float %src)
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%fneg.fabs.src = fneg float %fabs.src
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %fneg.fabs.src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_copysign_frexp_exp_f32:
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; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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define amdgpu_kernel void @s_test_copysign_frexp_exp_f32(ptr addrspace(1) %out, float %src, float %sign) #1 {
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%copysign = call float @llvm.copysign.f32(float %src, float %sign)
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %copysign)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_frexp_exp_f64:
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; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @s_test_frexp_exp_f64(ptr addrspace(1) %out, double %src) #1 {
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_fabs_frexp_exp_f64:
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; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @s_test_fabs_frexp_exp_f64(ptr addrspace(1) %out, double %src) #1 {
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%fabs.src = call double @llvm.fabs.f64(double %src)
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %fabs.src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_exp_f64:
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; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @s_test_fneg_fabs_frexp_exp_f64(ptr addrspace(1) %out, double %src) #1 {
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%fabs.src = call double @llvm.fabs.f64(double %src)
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%fneg.fabs.src = fneg double %fabs.src
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%frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %fneg.fabs.src)
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store i32 %frexp.exp, ptr addrspace(1) %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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