9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
231 lines
9.0 KiB
LLVM
231 lines
9.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX900
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX90A
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; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX940
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX10
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX900-GISEL
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declare void @llvm.amdgcn.global.load.lds(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture %lptr, i32 %size, i32 %offset, i32 %aux)
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define amdgpu_ps void @global_load_lds_dword_vaddr(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture %lptr) {
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; GFX900-LABEL: global_load_lds_dword_vaddr:
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; GFX900: ; %bb.0: ; %main_body
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; GFX900-NEXT: v_readfirstlane_b32 s0, v2
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; GFX900-NEXT: s_mov_b32 m0, s0
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; GFX900-NEXT: s_nop 0
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; GFX900-NEXT: global_load_dword v[0:1], off offset:16 glc lds
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; GFX900-NEXT: s_endpgm
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;
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; GFX90A-LABEL: global_load_lds_dword_vaddr:
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; GFX90A: ; %bb.0: ; %main_body
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; GFX90A-NEXT: v_readfirstlane_b32 s0, v2
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; GFX90A-NEXT: s_mov_b32 m0, s0
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; GFX90A-NEXT: s_nop 0
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; GFX90A-NEXT: global_load_dword v[0:1], off offset:16 glc lds
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; GFX90A-NEXT: s_endpgm
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;
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; GFX940-LABEL: global_load_lds_dword_vaddr:
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; GFX940: ; %bb.0: ; %main_body
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; GFX940-NEXT: v_readfirstlane_b32 s0, v2
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; GFX940-NEXT: s_mov_b32 m0, s0
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; GFX940-NEXT: s_nop 0
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; GFX940-NEXT: global_load_lds_dword v[0:1], off offset:16 sc0
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; GFX940-NEXT: s_endpgm
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;
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; GFX10-LABEL: global_load_lds_dword_vaddr:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: v_readfirstlane_b32 s0, v2
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; GFX10-NEXT: s_mov_b32 m0, s0
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; GFX10-NEXT: global_load_dword v[0:1], off offset:16 glc lds
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; GFX10-NEXT: s_endpgm
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;
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; GFX900-GISEL-LABEL: global_load_lds_dword_vaddr:
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; GFX900-GISEL: ; %bb.0: ; %main_body
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; GFX900-GISEL-NEXT: v_readfirstlane_b32 m0, v2
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; GFX900-GISEL-NEXT: s_nop 4
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; GFX900-GISEL-NEXT: global_load_dword v[0:1], off offset:16 glc lds
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; GFX900-GISEL-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 4, i32 16, i32 1)
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ret void
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}
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define amdgpu_ps void @global_load_lds_dword_saddr(ptr addrspace(1) nocapture inreg %gptr, ptr addrspace(3) nocapture %lptr) {
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; GFX900-LABEL: global_load_lds_dword_saddr:
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; GFX900: ; %bb.0: ; %main_body
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; GFX900-NEXT: v_readfirstlane_b32 s2, v0
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; GFX900-NEXT: v_mov_b32_e32 v1, 0
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; GFX900-NEXT: s_mov_b32 m0, s2
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; GFX900-NEXT: s_nop 0
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; GFX900-NEXT: global_load_dword v1, s[0:1] offset:32 slc lds
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; GFX900-NEXT: s_endpgm
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;
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; GFX90A-LABEL: global_load_lds_dword_saddr:
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; GFX90A: ; %bb.0: ; %main_body
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; GFX90A-NEXT: v_readfirstlane_b32 s2, v0
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; GFX90A-NEXT: v_mov_b32_e32 v1, 0
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; GFX90A-NEXT: s_mov_b32 m0, s2
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; GFX90A-NEXT: s_nop 0
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; GFX90A-NEXT: global_load_dword v1, s[0:1] offset:32 slc lds
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; GFX90A-NEXT: s_endpgm
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;
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; GFX940-LABEL: global_load_lds_dword_saddr:
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; GFX940: ; %bb.0: ; %main_body
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; GFX940-NEXT: v_readfirstlane_b32 s2, v0
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; GFX940-NEXT: v_mov_b32_e32 v1, 0
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; GFX940-NEXT: s_mov_b32 m0, s2
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; GFX940-NEXT: s_nop 0
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; GFX940-NEXT: global_load_lds_dword v1, s[0:1] offset:32 nt
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; GFX940-NEXT: s_endpgm
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;
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; GFX10-LABEL: global_load_lds_dword_saddr:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: v_readfirstlane_b32 s2, v0
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: s_mov_b32 m0, s2
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; GFX10-NEXT: global_load_dword v0, s[0:1] offset:32 slc lds
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; GFX10-NEXT: s_endpgm
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;
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; GFX900-GISEL-LABEL: global_load_lds_dword_saddr:
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; GFX900-GISEL: ; %bb.0: ; %main_body
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; GFX900-GISEL-NEXT: v_readfirstlane_b32 m0, v0
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; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0
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; GFX900-GISEL-NEXT: s_nop 3
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; GFX900-GISEL-NEXT: global_load_dword v0, s[0:1] offset:32 slc lds
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; GFX900-GISEL-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 4, i32 32, i32 2)
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ret void
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}
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define amdgpu_ps void @global_load_lds_dword_saddr_and_vaddr(ptr addrspace(1) nocapture inreg %gptr, ptr addrspace(3) nocapture %lptr, i32 %voffset) {
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; GFX900-LABEL: global_load_lds_dword_saddr_and_vaddr:
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; GFX900: ; %bb.0: ; %main_body
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; GFX900-NEXT: v_readfirstlane_b32 s2, v0
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; GFX900-NEXT: s_mov_b32 m0, s2
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; GFX900-NEXT: s_nop 0
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; GFX900-NEXT: global_load_dword v1, s[0:1] offset:48 lds
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; GFX900-NEXT: s_endpgm
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;
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; GFX90A-LABEL: global_load_lds_dword_saddr_and_vaddr:
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; GFX90A: ; %bb.0: ; %main_body
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; GFX90A-NEXT: v_readfirstlane_b32 s2, v0
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; GFX90A-NEXT: s_mov_b32 m0, s2
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; GFX90A-NEXT: s_nop 0
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; GFX90A-NEXT: global_load_dword v1, s[0:1] offset:48 scc lds
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; GFX90A-NEXT: s_endpgm
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;
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; GFX940-LABEL: global_load_lds_dword_saddr_and_vaddr:
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; GFX940: ; %bb.0: ; %main_body
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; GFX940-NEXT: v_readfirstlane_b32 s2, v0
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; GFX940-NEXT: s_mov_b32 m0, s2
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; GFX940-NEXT: s_nop 0
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; GFX940-NEXT: global_load_lds_dword v1, s[0:1] offset:48 sc1
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; GFX940-NEXT: s_endpgm
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;
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; GFX10-LABEL: global_load_lds_dword_saddr_and_vaddr:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: v_readfirstlane_b32 s2, v0
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; GFX10-NEXT: s_mov_b32 m0, s2
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; GFX10-NEXT: global_load_dword v1, s[0:1] offset:48 lds
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; GFX10-NEXT: s_endpgm
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;
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; GFX900-GISEL-LABEL: global_load_lds_dword_saddr_and_vaddr:
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; GFX900-GISEL: ; %bb.0: ; %main_body
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; GFX900-GISEL-NEXT: v_readfirstlane_b32 m0, v0
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; GFX900-GISEL-NEXT: s_nop 4
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; GFX900-GISEL-NEXT: global_load_dword v1, s[0:1] offset:48 lds
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; GFX900-GISEL-NEXT: s_endpgm
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main_body:
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%voffset.64 = zext i32 %voffset to i64
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%gep = getelementptr i8, ptr addrspace(1) %gptr, i64 %voffset.64
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call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gep, ptr addrspace(3) %lptr, i32 4, i32 48, i32 16)
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ret void
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}
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define amdgpu_ps void @global_load_lds_ushort_vaddr(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture %lptr) {
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; GFX900-LABEL: global_load_lds_ushort_vaddr:
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; GFX900: ; %bb.0: ; %main_body
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; GFX900-NEXT: v_readfirstlane_b32 s0, v2
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; GFX900-NEXT: s_mov_b32 m0, s0
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; GFX900-NEXT: s_nop 0
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; GFX900-NEXT: global_load_ushort v[0:1], off lds
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; GFX900-NEXT: s_endpgm
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;
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; GFX90A-LABEL: global_load_lds_ushort_vaddr:
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; GFX90A: ; %bb.0: ; %main_body
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; GFX90A-NEXT: v_readfirstlane_b32 s0, v2
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; GFX90A-NEXT: s_mov_b32 m0, s0
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; GFX90A-NEXT: s_nop 0
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; GFX90A-NEXT: global_load_ushort v[0:1], off lds
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; GFX90A-NEXT: s_endpgm
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;
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; GFX940-LABEL: global_load_lds_ushort_vaddr:
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; GFX940: ; %bb.0: ; %main_body
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; GFX940-NEXT: v_readfirstlane_b32 s0, v2
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; GFX940-NEXT: s_mov_b32 m0, s0
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; GFX940-NEXT: s_nop 0
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; GFX940-NEXT: global_load_lds_ushort v[0:1], off
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; GFX940-NEXT: s_endpgm
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;
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; GFX10-LABEL: global_load_lds_ushort_vaddr:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: v_readfirstlane_b32 s0, v2
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; GFX10-NEXT: s_mov_b32 m0, s0
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; GFX10-NEXT: global_load_ushort v[0:1], off dlc lds
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; GFX10-NEXT: s_endpgm
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;
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; GFX900-GISEL-LABEL: global_load_lds_ushort_vaddr:
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; GFX900-GISEL: ; %bb.0: ; %main_body
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; GFX900-GISEL-NEXT: v_readfirstlane_b32 m0, v2
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; GFX900-GISEL-NEXT: s_nop 4
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; GFX900-GISEL-NEXT: global_load_ushort v[0:1], off lds
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; GFX900-GISEL-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 2, i32 0, i32 4)
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ret void
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}
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define amdgpu_ps void @global_load_lds_ubyte_vaddr(ptr addrspace(1) nocapture %gptr, ptr addrspace(3) nocapture %lptr) {
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; GFX900-LABEL: global_load_lds_ubyte_vaddr:
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; GFX900: ; %bb.0: ; %main_body
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; GFX900-NEXT: v_readfirstlane_b32 s0, v2
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; GFX900-NEXT: s_mov_b32 m0, s0
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; GFX900-NEXT: s_nop 0
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; GFX900-NEXT: global_load_ubyte v[0:1], off lds
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; GFX900-NEXT: s_endpgm
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;
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; GFX90A-LABEL: global_load_lds_ubyte_vaddr:
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; GFX90A: ; %bb.0: ; %main_body
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; GFX90A-NEXT: v_readfirstlane_b32 s0, v2
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; GFX90A-NEXT: s_mov_b32 m0, s0
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; GFX90A-NEXT: s_nop 0
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; GFX90A-NEXT: global_load_ubyte v[0:1], off lds
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; GFX90A-NEXT: s_endpgm
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;
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; GFX940-LABEL: global_load_lds_ubyte_vaddr:
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; GFX940: ; %bb.0: ; %main_body
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; GFX940-NEXT: v_readfirstlane_b32 s0, v2
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; GFX940-NEXT: s_mov_b32 m0, s0
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; GFX940-NEXT: s_nop 0
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; GFX940-NEXT: global_load_lds_ubyte v[0:1], off
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; GFX940-NEXT: s_endpgm
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;
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; GFX10-LABEL: global_load_lds_ubyte_vaddr:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: v_readfirstlane_b32 s0, v2
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; GFX10-NEXT: s_mov_b32 m0, s0
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; GFX10-NEXT: global_load_ubyte v[0:1], off lds
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; GFX10-NEXT: s_endpgm
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;
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; GFX900-GISEL-LABEL: global_load_lds_ubyte_vaddr:
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; GFX900-GISEL: ; %bb.0: ; %main_body
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; GFX900-GISEL-NEXT: v_readfirstlane_b32 m0, v2
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; GFX900-GISEL-NEXT: s_nop 4
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; GFX900-GISEL-NEXT: global_load_ubyte v[0:1], off lds
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; GFX900-GISEL-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 1, i32 0, i32 0)
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ret void
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}
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