9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
71 lines
2.7 KiB
LLVM
71 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
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declare i32 @llvm.amdgcn.permlane64(i32)
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declare i32 @llvm.amdgcn.workitem.id.x()
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define amdgpu_kernel void @test_s(ptr addrspace(1) %out, i32 %src0) {
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; GFX11-LABEL: test_s:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_permlane64_b32 v0, v0
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; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%v = call i32 @llvm.amdgcn.permlane64(i32 %src0)
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store i32 %v, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_i(ptr addrspace(1) %out) {
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; GFX11-LABEL: test_i:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-NEXT: v_dual_mov_b32 v0, 0x63 :: v_dual_mov_b32 v1, 0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_permlane64_b32 v0, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%v = call i32 @llvm.amdgcn.permlane64(i32 99)
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store i32 %v, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_v(ptr addrspace(1) %out, i32 %src0) #1 {
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; GFX11-SDAG-LABEL: test_v:
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; GFX11-SDAG: ; %bb.0:
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; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-SDAG-NEXT: v_permlane64_b32 v0, v0
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; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-SDAG-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-SDAG-NEXT: s_nop 0
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; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-SDAG-NEXT: s_endpgm
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;
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; GFX11-GISEL-LABEL: test_v:
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; GFX11-GISEL: ; %bb.0:
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; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-GISEL-NEXT: v_permlane64_b32 v0, v0
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; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-GISEL-NEXT: s_nop 0
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; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-GISEL-NEXT: s_endpgm
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%tidx = call i32 @llvm.amdgcn.workitem.id.x()
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%v = call i32 @llvm.amdgcn.permlane64(i32 %tidx)
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store i32 %v, ptr addrspace(1) %out
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ret void
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}
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