9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
179 lines
6.0 KiB
LLVM
179 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
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declare i32 @llvm.amdgcn.s.quadmask.i32(i32)
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declare i64 @llvm.amdgcn.s.quadmask.i64(i64)
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define i32 @test_quadmask_constant_zero_i32() {
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; GFX11-LABEL: test_quadmask_constant_zero_i32:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mov_b32_e32 v0, 0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 0)
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ret i32 %qm
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}
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define i32 @test_quadmask_constant_neg_one_i32() {
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; GFX11-LABEL: test_quadmask_constant_neg_one_i32:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mov_b32_e32 v0, 0xff
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 -1)
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ret i32 %qm
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}
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define i32 @test_quadmask_constant_undef_i32() {
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; GFX11-LABEL: test_quadmask_constant_undef_i32:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_quadmask_b32 s0, s0
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; GFX11-NEXT: v_mov_b32_e32 v0, s0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 undef)
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ret i32 %qm
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}
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define i32 @test_quadmask_constant_poison_i32() {
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; GFX11-LABEL: test_quadmask_constant_poison_i32:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_quadmask_b32 s0, s0
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; GFX11-NEXT: v_mov_b32_e32 v0, s0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 poison)
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ret i32 %qm
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}
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define i32 @test_quadmask_constant_i32() {
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; GFX11-LABEL: test_quadmask_constant_i32:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mov_b32_e32 v0, 0xcb
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 u0x85003092)
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ret i32 %qm
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}
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define amdgpu_cs void @test_quadmask_sgpr_i32(i32 inreg %mask, ptr addrspace(1) %out) {
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; GFX11-LABEL: test_quadmask_sgpr_i32:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_quadmask_b32 s0, s0
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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entry:
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%qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 %mask)
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store i32 %qm, ptr addrspace(1) %out
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ret void
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}
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define i32 @test_quadmask_vgpr_i32(i32 %mask) {
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; GFX11-LABEL: test_quadmask_vgpr_i32:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v0
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; GFX11-NEXT: s_quadmask_b32 s0, s0
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; GFX11-NEXT: v_mov_b32_e32 v0, s0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i32 @llvm.amdgcn.s.quadmask.i32(i32 %mask)
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ret i32 %qm
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}
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define i64 @test_quadmask_constant_i64() {
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; GFX11-LABEL: test_quadmask_constant_i64:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, 0xe3e6 :: v_dual_mov_b32 v1, 0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 u0x67D000FC85F00A90)
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ret i64 %qm
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}
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define i64 @test_quadmask_constant_zero_i64() {
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; GFX11-LABEL: test_quadmask_constant_zero_i64:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 0)
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ret i64 %qm
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}
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define i64 @test_quadmask_constant_neg_one_i64() {
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; GFX11-LABEL: test_quadmask_constant_neg_one_i64:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, 0xffff :: v_dual_mov_b32 v1, 0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 -1)
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ret i64 %qm
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}
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define i64 @test_quadmask_constant_undef_i64() {
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; GFX11-LABEL: test_quadmask_constant_undef_i64:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_quadmask_b64 s[0:1], s[0:1]
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; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 undef)
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ret i64 %qm
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}
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define i64 @test_quadmask_constant_poison_i64() {
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; GFX11-LABEL: test_quadmask_constant_poison_i64:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_quadmask_b64 s[0:1], s[0:1]
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; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 poison)
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ret i64 %qm
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}
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define amdgpu_cs void @test_quadmask_sgpr_i64(i64 inreg %mask, ptr addrspace(1) %out) {
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; GFX11-LABEL: test_quadmask_sgpr_i64:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_quadmask_b64 s[0:1], s[0:1]
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; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
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; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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entry:
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%qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 %mask)
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store i64 %qm, ptr addrspace(1) %out
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ret void
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}
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define i64 @test_quadmask_vgpr_i64(i64 %mask) {
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; GFX11-LABEL: test_quadmask_vgpr_i64:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_readfirstlane_b32 s0, v0
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; GFX11-NEXT: v_readfirstlane_b32 s1, v1
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; GFX11-NEXT: s_quadmask_b64 s[0:1], s[0:1]
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; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%qm = call i64 @llvm.amdgcn.s.quadmask.i64(i64 %mask)
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ret i64 %qm
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}
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