9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
53 lines
2.4 KiB
LLVM
53 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s
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define amdgpu_gs void @test_fptrunc_round_upward(float %a, i32 %data0, <4 x i32> %data1, ptr addrspace(1) %out) {
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; CHECK-LABEL: test_fptrunc_round_upward:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
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; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0
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; CHECK-NEXT: global_store_short v[6:7], v0, off
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; CHECK-NEXT: s_endpgm
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%res = call half @llvm.fptrunc.round(float %a, metadata !"round.upward")
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store half %res, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_gs void @test_fptrunc_round_downward(float %a, i32 %data0, <4 x i32> %data1, ptr addrspace(1) %out) {
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; CHECK-LABEL: test_fptrunc_round_downward:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1
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; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0
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; CHECK-NEXT: global_store_short v[6:7], v0, off
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; CHECK-NEXT: s_endpgm
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%res = call half @llvm.fptrunc.round(float %a, metadata !"round.downward")
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store half %res, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_gs void @test_fptrunc_round_upward_multiple_calls(float %a, float %b, i32 %data0, <4 x i32> %data1, ptr addrspace(1) %out) {
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; CHECK-LABEL: test_fptrunc_round_upward_multiple_calls:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
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; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0
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; CHECK-NEXT: v_cvt_f16_f32_e32 v2, v1
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; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2
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; CHECK-NEXT: v_cvt_f16_f32_e32 v1, v1
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; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0
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; CHECK-NEXT: v_add_f16_e32 v0, v0, v2
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; CHECK-NEXT: v_add_f16_e32 v0, v1, v0
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; CHECK-NEXT: global_store_short v[7:8], v0, off
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; CHECK-NEXT: s_endpgm
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%res1 = call half @llvm.fptrunc.round(float %a, metadata !"round.upward")
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%res2 = call half @llvm.fptrunc.round(float %b, metadata !"round.upward")
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%res3 = call half @llvm.fptrunc.round(float %b, metadata !"round.downward")
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%res4 = fadd half %res1, %res2
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%res5 = fadd half %res3, %res4
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store half %res5, ptr addrspace(1) %out, align 4
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ret void
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}
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declare half @llvm.fptrunc.round(float, metadata)
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