9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
156 lines
5.5 KiB
YAML
156 lines
5.5 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck %s
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# The purpose of this test is to make sure we are combining relevant memory
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# operations correctly with/without SCC bit.
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--- |
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define amdgpu_kernel void @test1(ptr addrspace(1) %out) {
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%out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1
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store i32 123, ptr addrspace(1) %out.gep.1
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store i32 456, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test2(ptr addrspace(1) %out) {
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%out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1
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store i32 123, ptr addrspace(1) %out.gep.1
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store i32 456, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test3(ptr addrspace(1) %out) {
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%out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1
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store i32 123, ptr addrspace(1) %out.gep.1
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store i32 456, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test4(ptr addrspace(1) %out) {
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%out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 1
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store i32 123, ptr addrspace(1) %out.gep.1
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store i32 456, ptr addrspace(1) %out
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ret void
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}
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...
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# CHECK: BUFFER_STORE_DWORDX2_OFFSET killed %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 0, 0, implicit $exec :: (store (s64) into %ir.out.gep.1, align 4, addrspace 1)
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---
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name: test1
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 123, implicit $exec
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$vgpr1 = V_MOV_B32_e32 456, implicit $exec
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$sgpr2 = S_MOV_B32 -1
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$sgpr3 = S_MOV_B32 61440
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `ptr addrspace(4) undef`, addrspace 4)
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%2:sgpr_32 = COPY $sgpr2
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%3:sgpr_32 = COPY $sgpr3
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%4:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %2, %subreg.sub1, %3, %subreg.sub2
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%5:vgpr_32 = COPY $vgpr0
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%6:vgpr_32 = COPY $vgpr1
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BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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S_ENDPGM 0
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...
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# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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---
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name: test2
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 123, implicit $exec
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$vgpr1 = V_MOV_B32_e32 456, implicit $exec
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$sgpr2 = S_MOV_B32 -1
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$sgpr3 = S_MOV_B32 61440
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `ptr addrspace(4) undef`, addrspace 4)
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%2:sgpr_32 = COPY $sgpr2
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%3:sgpr_32 = COPY $sgpr3
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%4:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %2, %subreg.sub1, %3, %subreg.sub2
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%5:vgpr_32 = COPY $vgpr0
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%6:vgpr_32 = COPY $vgpr1
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BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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S_ENDPGM 0
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...
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# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 8, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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---
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name: test3
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 123, implicit $exec
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$vgpr1 = V_MOV_B32_e32 456, implicit $exec
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$sgpr2 = S_MOV_B32 -1
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$sgpr3 = S_MOV_B32 61440
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `ptr addrspace(4) undef`, addrspace 4)
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%2:sgpr_32 = COPY $sgpr2
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%3:sgpr_32 = COPY $sgpr3
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%4:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %2, %subreg.sub1, %3, %subreg.sub2
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%5:vgpr_32 = COPY $vgpr0
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%6:vgpr_32 = COPY $vgpr1
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BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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S_ENDPGM 0
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...
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# CHECK: BUFFER_STORE_DWORDX2_OFFSET killed %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 16, 0, implicit $exec :: (store (s64) into %ir.out.gep.1, align 4, addrspace 1)
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---
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name: test4
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $sgpr0_sgpr1
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$vgpr0 = V_MOV_B32_e32 123, implicit $exec
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$vgpr1 = V_MOV_B32_e32 456, implicit $exec
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$sgpr2 = S_MOV_B32 -1
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$sgpr3 = S_MOV_B32 61440
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%0:sgpr_64 = COPY $sgpr0_sgpr1
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%1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `ptr addrspace(4) undef`, addrspace 4)
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%2:sgpr_32 = COPY $sgpr2
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%3:sgpr_32 = COPY $sgpr3
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%4:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %2, %subreg.sub1, %3, %subreg.sub2
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%5:vgpr_32 = COPY $vgpr0
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%6:vgpr_32 = COPY $vgpr1
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BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)
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S_ENDPGM 0
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...
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