9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
103 lines
3.2 KiB
YAML
103 lines
3.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=si-optimize-exec-masking -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-optimize-exec-masking -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: lower_term_opcodes
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tracksRegLiveness: false
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body: |
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; CHECK-LABEL: name: lower_term_opcodes
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0 = COPY $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0 = S_MOV_B32 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0 = S_MOV_B32 &SYMBOL
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0_sgpr1 = COPY $sgpr2_sgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: successors: %bb.5(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0_sgpr1 = S_MOV_B64 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.5:
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; CHECK-NEXT: successors: %bb.6(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0_sgpr1 = S_MOV_B64 &SYMBOL
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.6:
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; CHECK-NEXT: successors: %bb.7(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0 = S_XOR_B32 $sgpr1, $sgpr2, implicit-def $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.7:
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; CHECK-NEXT: successors: %bb.8(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.8:
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; CHECK-NEXT: successors: %bb.9(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0 = S_OR_B32 $sgpr1, $sgpr2, implicit-def $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.9:
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; CHECK-NEXT: successors: %bb.10(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0_sgpr1 = S_OR_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.10:
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; CHECK-NEXT: successors: %bb.11(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr0 = S_ANDN2_B32 $sgpr1, $sgpr2, implicit-def $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.11:
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; CHECK-NEXT: $sgpr0_sgpr1 = S_ANDN2_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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bb.0:
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$sgpr0 = S_MOV_B32_term $sgpr1
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bb.1:
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$sgpr0 = S_MOV_B32_term 0
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bb.3:
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$sgpr0 = S_MOV_B32_term &SYMBOL
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bb.4:
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$sgpr0_sgpr1 = S_MOV_B64_term $sgpr2_sgpr3
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bb.5:
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$sgpr0_sgpr1 = S_MOV_B64_term 0
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bb.6:
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$sgpr0_sgpr1 = S_MOV_B64_term &SYMBOL
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bb.7:
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$sgpr0 = S_XOR_B32_term $sgpr1, $sgpr2, implicit-def $scc
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bb.8:
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$sgpr0_sgpr1 = S_XOR_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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bb.9:
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$sgpr0 = S_OR_B32_term $sgpr1, $sgpr2, implicit-def $scc
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bb.10:
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$sgpr0_sgpr1 = S_OR_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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bb.11:
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$sgpr0 = S_ANDN2_B32_term $sgpr1, $sgpr2, implicit-def $scc
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bb.12:
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$sgpr0_sgpr1 = S_ANDN2_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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...
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